Simulation Results: otbn

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.40 %
  • code
  • 95.31 %
  • assert
  • 90.43 %
  • func
  • 97.46 %
  • block
  • 99.40 %
  • line
  • 99.54 %
  • branch
  • 92.36 %
  • toggle
  • 91.80 %
  • FSM
  • 97.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 227.646us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 45.983us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 15.020us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 5.000s 24.945us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 60.920us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 6.000s 90.341us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 15.020us 1 1 100.00
otbn_csr_aliasing 4.000s 60.920us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 58.000s 2684.588us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 50.000s 1102.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 30.000s 411.631us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 337.997us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 105.000s 539.466us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 36.000s 118.890us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 7.000s 21.428us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 45.740us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 16.821us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 20.367us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 18.973us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 23.129us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 23.129us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 45.983us 1 1 100.00
otbn_csr_rw 4.000s 15.020us 1 1 100.00
otbn_csr_aliasing 4.000s 60.920us 1 1 100.00
otbn_same_csr_outstanding 4.000s 20.639us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 45.983us 1 1 100.00
otbn_csr_rw 4.000s 15.020us 1 1 100.00
otbn_csr_aliasing 4.000s 60.920us 1 1 100.00
otbn_same_csr_outstanding 4.000s 20.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 7.000s 52.237us 1 1 100.00
otbn_dmem_err 8.000s 74.842us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 214.609us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 211.018us 1 1 100.00
otbn_mac_bignum_acc_err 8.000s 58.751us 1 1 100.00
otbn_urnd_err 5.000s 16.542us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 6.000s 32.744us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 13.706us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 4.000s 27.337us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
otbn_tl_intg_err 18.000s 120.813us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 64.000s 278.559us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 227.646us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 74.842us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 7.000s 52.237us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 120.813us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 21.428us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 52.237us 1 1 100.00
otbn_dmem_err 8.000s 74.842us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 45.740us 1 1 100.00
otbn_illegal_mem_acc 6.000s 32.744us 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 52.237us 1 1 100.00
otbn_dmem_err 8.000s 74.842us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 45.740us 1 1 100.00
otbn_illegal_mem_acc 6.000s 32.744us 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 7.000s 21.428us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 7.000s 52.237us 1 1 100.00
otbn_dmem_err 8.000s 74.842us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 45.740us 1 1 100.00
otbn_illegal_mem_acc 6.000s 32.744us 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 156.982us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 67.932us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 20.000s 184.004us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 20.000s 184.004us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 19.759us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 16.000s 60.895us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 22.785us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 8.000s 22.785us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 13.250us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 105.000s 539.466us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 11.000s 148.753us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 55.730us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 114.000s 2352.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 114.000s 1487.485us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 206.497us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 47752197480495483710884090432611581713515935475384172525165438881833706799009 262
UVM_INFO @ 1487485350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---