Simulation Results: otp_ctrl

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.60 %
  • code
  • 70.22 %
  • assert
  • 93.65 %
  • func
  • 53.92 %
  • line
  • 87.03 %
  • branch
  • 83.43 %
  • cond
  • 85.51 %
  • toggle
  • 61.38 %
  • FSM
  • 33.77 %
Validation stages
V1
100.00%
V2
60.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.720s 109.983us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.680s 320.114us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.590s 853.352us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.850s 274.482us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.850s 913.380us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.310s 133.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.590s 853.352us 1 1 100.00
otp_ctrl_csr_aliasing 5.850s 913.380us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.440s 634.548us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.670s 42.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 117.920s 6611.112us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.760s 2722.015us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.170s 145.748us 0 1 0.00
otp_ctrl_check_fail 15.240s 955.551us 0 1 0.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 2.990s 157.045us 0 1 0.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 2.940s 171.412us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 18.000s 1397.608us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 49.750s 5587.920us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 7.510s 342.013us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 30.120s 20053.112us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 25.450s 4143.865us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.730s 98.371us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.290s 102.671us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.220s 97.666us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.220s 97.666us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.680s 320.114us 1 1 100.00
otp_ctrl_csr_rw 2.590s 853.352us 1 1 100.00
otp_ctrl_csr_aliasing 5.850s 913.380us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.430s 209.041us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.680s 320.114us 1 1 100.00
otp_ctrl_csr_rw 2.590s 853.352us 1 1 100.00
otp_ctrl_csr_aliasing 5.850s 913.380us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.430s 209.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
otp_ctrl_tl_intg_err 32.700s 23849.901us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 32.700s 23849.901us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_macro_errs 7.510s 342.013us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_macro_errs 7.510s 342.013us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.750s 697.275us 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.760s 2722.015us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 15.240s 955.551us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 7.300s 819.949us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 296.730s 78043.765us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 2.990s 157.045us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.490s 1637.560us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 7.510s 342.013us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 65.980s 21889.585us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 3.200s 137.534us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 105678353423995162497830147632177162367254631247457467544557257065803638633219 2834
UVM_INFO @ 145747699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 50273763464444517039733101566183713701205098308496882859588819956607411135684 2782
UVM_INFO @ 171412346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 93610297610937757506987519830887010968095603418849278158369820576135897703792 14869
UVM_INFO @ 20053111721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72469918415009872323669516500757980629126136085733903307171906329103284836889 306
UVM_INFO @ 137533626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 2 test runs
otp_ctrl_dai_lock 79434643989438150733297100281822755193563853574029421915080537969440947652894 4951
UVM_INFO @ 819949231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 70338165661898712722939809897955720593527413607011964966911650556309855540974 12864
UVM_INFO @ 955551062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 90256762864892210080315839965659753618450132043499894642049312586080942093348 113187
UVM_INFO @ 6611112380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 44732012971354945689902115491217261871885993023424961177324483811625392751525 89
UVM_INFO @ 21889585362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 36756749569275081832574560795364337739001037617438814524659892730644623517357 962
UVM_INFO @ 157044800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 110961814569849898764679353707234276553539159560872515249673508296167887006670 20521
UVM_INFO @ 4143864942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---