Simulation Results: rom_ctrl/64kb

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.01 %
  • code
  • 94.52 %
  • assert
  • 96.79 %
  • func
  • 96.71 %
  • block
  • 96.63 %
  • line
  • 97.22 %
  • branch
  • 93.82 %
  • toggle
  • 87.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 305.622us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 548.973us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 386.461us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 4976.475us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 379.384us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.000s 301.225us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 386.461us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 379.384us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 1023.958us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 728.106us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.000s 391.598us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.000s 10114.664us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 11.000s 2283.620us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 212.388us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 300.428us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 300.428us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 548.973us 1 1 100.00
rom_ctrl_csr_rw 5.000s 386.461us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 379.384us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 286.598us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 7.000s 548.973us 1 1 100.00
rom_ctrl_csr_rw 5.000s 386.461us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 379.384us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 286.598us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 13808.324us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 2252.806us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 305.622us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 305.622us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 305.622us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 27.000s 2252.806us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
rom_ctrl_kmac_err_chk 11.000s 2283.620us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 73.000s 39335.087us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 13808.324us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 208.000s 703.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 32.000s 3981.687us 1 1 100.00