Simulation Results: rstmgr

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.22 %
  • code
  • 99.32 %
  • assert
  • 98.35 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.080s 59.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.170s 65.954us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.300s 219.783us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.620s 53.961us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.090s 68.298us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00
rstmgr_csr_aliasing 1.620s 53.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.020s 93.817us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.880s 42.546us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.990s 82.386us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.030s 631.542us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.030s 631.542us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.030s 631.542us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.030s 631.542us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 36.010s 5422.271us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.960s 40.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.640s 83.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.640s 83.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.170s 65.954us 1 1 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00
rstmgr_csr_aliasing 1.620s 53.961us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 40.578us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.170s 65.954us 1 1 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00
rstmgr_csr_aliasing 1.620s 53.961us 1 1 100.00
rstmgr_same_csr_outstanding 1.150s 40.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 18.270s 3666.552us 1 1 100.00
rstmgr_tl_intg_err 2.880s 328.186us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 18.270s 3666.552us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 18.270s 3666.552us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.880s 328.186us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.250s 57.384us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.670s 460.240us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.000s 291.633us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 18.270s 3666.552us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.070s 37.770us 1 1 100.00