Simulation Results

Simulation Results: rv_dm/use_dmi_interface

25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
88.15 %

code
75.12 %

assert
96.43 %

func
92.90 %

block
89.97 %

line
89.93 %

branch
72.78 %

toggle
75.26 %

FSM
62.50 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	32.000s	921.227us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	36.000s	724.946us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	32.000s	424.324us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	36.000s	10910.801us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	33.000s	540.162us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	33.000s	3369.487us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	53.000s	10740.164us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	42.000s	14526.234us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	414.000s	270289.701us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	576.949us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	32.000s	962.968us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	177.748us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	33.000s	179.697us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	34.000s	133.577us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	39.000s	556.065us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	32.000s	384.803us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	33.000s	1588.498us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	31.000s	576.949us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	31.000s	533.034us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	33.000s	354.822us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	31.000s	177.748us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	33.000s	99.025us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	32.000s	514.509us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	36.000s	178.790us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	52.000s	4301.985us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	46.000s	1863.806us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	33.000s	247.565us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	46.000s	1863.806us	1	1	100.00
	rv_dm_csr_rw	36.000s	178.790us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	31.000s	52.693us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	31.000s	31.683us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	32.000s	921.227us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	35.000s	233.140us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	36.000s	588.038us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	33.000s	678.314us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	570.552us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	57.000s	13470.019us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	32.000s	255.843us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	35.000s	2138.661us	0	1	0.00
sba_autoincrement				0	1	0.00
	rv_dm_autoincr_sba_tl_access	32.000s	74.229us	0	1	0.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	32.000s	94.464us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	36.000s	1258.617us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	35.000s	291.348us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	39.000s	136.531us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	49.000s	9332.282us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	74.000s	3240.313us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	32.000s	86.354us	1	1	100.00
stress_all				1	1	100.00
	rv_dm_stress_all	44.000s	8406.663us	1	1	100.00
alert_test				1	1	100.00
	rv_dm_alert_test	31.000s	154.906us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	33.000s	208.605us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	33.000s	208.605us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	1863.806us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	514.509us	1	1	100.00
	rv_dm_csr_rw	36.000s	178.790us	1	1	100.00
	rv_dm_same_csr_outstanding	37.000s	698.411us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	46.000s	1863.806us	1	1	100.00
	rv_dm_csr_hw_reset	32.000s	514.509us	1	1	100.00
	rv_dm_csr_rw	36.000s	178.790us	1	1	100.00
	rv_dm_same_csr_outstanding	37.000s	698.411us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	38.000s	3193.585us	1	1	100.00
	rv_dm_tl_intg_err	40.000s	1878.968us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	40.000s	1878.968us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	36.000s	1258.617us	1	1	100.00
	rv_dm_debug_disabled	31.000s	160.787us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	36.000s	1258.617us	1	1	100.00
	rv_dm_debug_disabled	31.000s	160.787us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	32.000s	921.227us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	291.556us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	166.096us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	30.000s	166.096us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	291.556us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	32.000s	3412.722us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	279.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	106835300074359100047341367615484556392186685347329468082021252671168631568001	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24112
	rv_dm_bad_sba_tl_access	62620800734572802920086757312821504350044904225692678399139846275619356528398	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24251
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				2 test runs
	rv_dm_delayed_resp_sba_tl_access	33422435225161565151125343134658925296063671146235209634457010256140776082576	107	UVM_INFO @ 255843291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	33596383351474435315408400802127695774900783824960532555573046545123838221774	107	UVM_INFO @ 74229159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				2 test runs
	rv_dm_mem_tl_access_resuming	43279671702832780608949859231898763446521489412634375047399065643595365114911	87	UVM_INFO @ 179696739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	41211878287941556344953533246622439915186665434106225468032339550238418320391	107	UVM_INFO @ 3412721583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				1 test run
	rv_dm_hart_unavail	92212018181517167211439966383121414612905877118893325757762078105264076113377	87	UVM_INFO @ 136530875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	93937149152053364964669633774886589302957197066276474521224736878144604718892	87	UVM_INFO @ 94463914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	109679251700004771643509242123224786874611103220955618878055242617025052005559	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---