Simulation Results: rv_timer

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.74 %
  • code
  • 95.85 %
  • assert
  • 97.78 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 2.000s 893.401us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 35.509us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 1.000s 34.817us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 1176.088us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 32.731us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 135.344us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 1.000s 34.817us 1 1 100.00
rv_timer_csr_aliasing 2.000s 32.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.000s 70.649us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 3913.786us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 268.000s 1068525.841us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 268.000s 1068525.841us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.000s 1300.160us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 25.341us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 70.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.000s 74.334us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.000s 74.334us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 35.509us 1 1 100.00
rv_timer_csr_rw 1.000s 34.817us 1 1 100.00
rv_timer_csr_aliasing 2.000s 32.731us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 57.270us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 35.509us 1 1 100.00
rv_timer_csr_rw 1.000s 34.817us 1 1 100.00
rv_timer_csr_aliasing 2.000s 32.731us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 57.270us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 122.684us 1 1 100.00
rv_timer_tl_intg_err 1.000s 111.339us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.000s 111.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 81.579us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 147.138us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 5.000s 2719.526us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 10732994059100619011164774517620072396021410937750212915433735487989566606494 84
UVM_INFO @ 81579199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 5326672474531723999001276320902674239913792060926602448068153428413174456121 84
UVM_INFO @ 70649253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 109560149237518101552178474952140355488001765421479854929772009917793306476261 84
UVM_INFO @ 147137673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---