Simulation Results: spi_device/1r1w

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.35 %
  • code
  • 91.36 %
  • assert
  • 95.39 %
  • func
  • 69.30 %
  • block
  • 98.30 %
  • line
  • 98.71 %
  • branch
  • 96.92 %
  • toggle
  • 81.25 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 110.000s 61602.571us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 51.776us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 4.000s 200.581us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 28.000s 2178.804us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 12.000s 4164.089us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 4.000s 449.864us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 4.000s 200.581us 1 1 100.00
spi_device_csr_aliasing 12.000s 4164.089us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 13.110us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 131.064us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 51.597us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 7.776us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.540us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 5.000s 80.500us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 5.000s 80.500us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.000s 720.862us 1 1 100.00
spi_device_tpm_sts_read 3.000s 208.785us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 53.000s 5867.087us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 27.000s 12829.829us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 634.889us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.000s 634.889us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 8.000s 2144.783us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 8.000s 2144.783us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 8.000s 2144.783us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 8.000s 2144.783us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 8.000s 2144.783us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 29.000s 14595.305us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 59.000s 17844.329us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 59.000s 17844.329us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 59.000s 17844.329us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.000s 1138.476us 1 1 100.00
spi_device_read_buffer_direct 7.000s 1427.157us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 59.000s 17844.329us 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 8.000s 180.667us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 13.000s 1825.291us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 13.000s 1825.291us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 110.000s 61602.571us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 41.000s 13070.976us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 392.233us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 39.516us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 26.751us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 65.588us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 65.588us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 51.776us 1 1 100.00
spi_device_csr_rw 4.000s 200.581us 1 1 100.00
spi_device_csr_aliasing 12.000s 4164.089us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 26.546us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 51.776us 1 1 100.00
spi_device_csr_rw 4.000s 200.581us 1 1 100.00
spi_device_csr_aliasing 12.000s 4164.089us 1 1 100.00
spi_device_same_csr_outstanding 2.000s 26.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 628.347us 1 1 100.00
spi_device_tl_intg_err 11.000s 292.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.000s 292.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 25.000s 5882.318us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 97941677844040345934113512511266851958542995253724630269586881412962138118800 87
UVM_ERROR @ 5428444 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[934] not found within the scope .
UVM_ERROR @ 5428444 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[934] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 31691436821997739271030479560697516023912318459117277862287240431385480148263 85
UVM_ERROR @ 1103345 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x442703 [10001000010011100000011] vs 0x0 [0])
UVM_ERROR @ 1121345 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4e072a [10011100000011100101010] vs 0x0 [0])
UVM_ERROR @ 1138345 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4f70d0 [10011110111000011010000] vs 0x0 [0])
UVM_ERROR @ 1157345 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2881bc [1010001000000110111100] vs 0x0 [0])