Simulation Results: spi_host

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.44 %
  • code
  • 95.03 %
  • assert
  • 94.89 %
  • func
  • 87.39 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 23.000s 3079.988us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 30.048us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 19.199us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 194.938us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 50.044us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 19.761us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 19.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 50.044us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 15.146us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 47.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 69.776us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 1211.734us 1 1 100.00
spi_host_error_cmd 1.000s 44.166us 1 1 100.00
spi_host_event 35.000s 8700.793us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 128.926us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 128.926us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 128.926us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 94.153us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 25.049us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 128.926us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 128.926us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 23.000s 3079.988us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 23.000s 3079.988us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 5.000s 228.128us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 526.981us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 51.000s 5632.412us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 146.119us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 1211.734us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 17.293us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 20.285us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 556.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 556.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.048us 1 1 100.00
spi_host_csr_rw 1.000s 19.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 50.044us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 57.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 30.048us 1 1 100.00
spi_host_csr_rw 1.000s 19.199us 1 1 100.00
spi_host_csr_aliasing 1.000s 50.044us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 57.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 1.000s 44.812us 1 1 100.00
spi_host_sec_cm 2.000s 50.501us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 44.812us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 125.000s 12363.047us 1 1 100.00