Simulation Results: sram_ctrl/main

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 96.50 %
  • assert
  • 97.96 %
  • func
  • 91.75 %
  • block
  • 95.68 %
  • line
  • 96.44 %
  • branch
  • 93.52 %
  • toggle
  • 96.04 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 1030.772us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 56.206us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.639us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 764.189us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 29.411us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 758.244us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 41.639us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 29.411us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 219.000s 24585.783us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 75.000s 1580.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 22.000s 13584.339us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 89.000s 2698.137us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 153.000s 60221.090us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 42.000s 11662.015us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5211.270us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 18.000s 6318.424us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 366.256us 1 1 100.00
sram_ctrl_partial_access_b2b 112.000s 4109.463us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 4.000s 2767.074us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.000s 1369.921us 1 1 100.00
sram_ctrl_throughput_w_readback 3.000s 1414.553us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 976.529us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 708.114us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 149.000s 10010.798us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 14.702us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 116.467us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 116.467us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 56.206us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.639us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 29.411us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.541us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 56.206us 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.639us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 29.411us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 43.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.000s 16024.834us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 642.300us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 642.300us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 976.529us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 976.529us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 41.639us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 18.000s 6318.424us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 18.000s 6318.424us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 18.000s 6318.424us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5211.270us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2809.191us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 16.000s 16024.834us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 9494.172us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1030.772us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 1030.772us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 18.000s 6318.424us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 16.000s 5211.270us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 1030.772us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 242.390us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 46.000s 4583.709us 1 1 100.00