Simulation Results: uart

 
25/05/2026 19:40:27 DVSim: v1.49.1 sha: f988e3e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.43 %
  • code
  • 77.39 %
  • assert
  • 97.69 %
  • func
  • 90.20 %
  • block
  • 98.41 %
  • line
  • 98.95 %
  • branch
  • 96.87 %
  • toggle
  • 88.74 %
  • FSM
  • 25.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 13.000s 5464.122us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 16.670us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 13.064us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 306.858us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 31.065us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 106.375us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 13.064us 1 1 100.00
uart_csr_aliasing 1.000s 31.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 7.000s 24428.473us 1 1 100.00
parity 2 2 100.00
uart_smoke 13.000s 5464.122us 1 1 100.00
uart_tx_rx 7.000s 24428.473us 1 1 100.00
parity_error 2 2 100.00
uart_intr 17.000s 11551.222us 1 1 100.00
uart_rx_parity_err 79.000s 99378.666us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 7.000s 24428.473us 1 1 100.00
uart_intr 17.000s 11551.222us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 11.000s 14343.592us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 4.000s 2620.121us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 65.000s 51346.331us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 17.000s 11551.222us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 17.000s 11551.222us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 17.000s 11551.222us 1 1 100.00
perf 1 1 100.00
uart_perf 62.000s 9586.826us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.000s 8190.227us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.000s 8190.227us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 43.000s 32787.868us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 7.000s 4140.398us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 3.000s 1554.172us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 41.000s 5884.629us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 396.000s 93972.539us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 287.000s 404317.948us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 2.000s 17.640us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 44.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 3.000s 156.423us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 3.000s 156.423us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.670us 1 1 100.00
uart_csr_rw 1.000s 13.064us 1 1 100.00
uart_csr_aliasing 1.000s 31.065us 1 1 100.00
uart_same_csr_outstanding 2.000s 15.082us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 16.670us 1 1 100.00
uart_csr_rw 1.000s 13.064us 1 1 100.00
uart_csr_aliasing 1.000s 31.065us 1 1 100.00
uart_same_csr_outstanding 2.000s 15.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 78.062us 1 1 100.00
uart_tl_intg_err 2.000s 168.981us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 168.981us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 54.000s 2582.733us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 1 test run
uart_noise_filter 4488788845582313119990778195019680653972896827188298253284990485632030256593 83
UVM_ERROR @ 231792202 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 231897462 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 272106782 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 272106782 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0