Simulation Results: aes/gcm_masked

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.25 %
  • code
  • 96.25 %
  • assert
  • 98.29 %
  • func
  • 64.22 %
  • block
  • 96.60 %
  • line
  • 97.72 %
  • branch
  • 91.80 %
  • toggle
  • 98.05 %
  • FSM
  • 97.42 %
Validation stages
V1
100.00%
V2
89.47%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 86.924us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 303.763us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 63.748us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 102.474us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 468.193us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 317.196us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 71.904us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 102.474us 1 1 100.00
aes_csr_aliasing 2.000s 317.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 303.763us 1 1 100.00
aes_config_error 3.000s 78.756us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 303.763us 1 1 100.00
aes_config_error 3.000s 78.756us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_b2b 5.000s 532.080us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 2.000s 303.763us 1 1 100.00
aes_config_error 3.000s 78.756us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 204.781us 1 1 100.00
aes_config_error 3.000s 78.756us 1 1 100.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 6.000s 684.017us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 2490.995us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 485.496us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
stress 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_sideload 3.000s 121.116us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 113.333us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 24.000s 1297.660us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 93.622us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 1.000s 73.858us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 92.031us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 92.031us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.748us 1 1 100.00
aes_csr_rw 1.000s 102.474us 1 1 100.00
aes_csr_aliasing 2.000s 317.196us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.131us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 63.748us 1 1 100.00
aes_csr_rw 1.000s 102.474us 1 1 100.00
aes_csr_aliasing 2.000s 317.196us 1 1 100.00
aes_same_csr_outstanding 2.000s 102.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 6.000s 119.678us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 4716.448us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 663.615us 1 1 100.00
aes_tl_intg_err 2.000s 335.900us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 335.900us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 2.000s 303.763us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
aes_core_fi 3.000s 154.827us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 93.622us 1 1 100.00
aes_config_error 3.000s 78.756us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_core_fi 3.000s 154.827us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 117.463us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 97.610us 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 119.101us 1 1 100.00
aes_sideload 3.000s 121.116us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 97.610us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 97.610us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 97.610us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 97.610us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 97.610us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 119.101us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 3602.069s 0.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_ctr_fi 2.000s 74.256us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 1.000s 129.095us 1 1 100.00
aes_fi 3601.000s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3601.000s 0.000us 0 1 0.00
aes_control_fi 3.000s 75.943us 1 1 100.00
aes_cipher_fi 3.000s 67.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 16.795us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_alert_reset 56106934930987806947861680067320912182726322545593814236039772706371311866725 None
aes_fi 41094321027445580767391518377958330107973341788108335800505301968806438763134 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 89410142048855539455377627187269589937486837485828690398153633975877778383409 33962
UVM_INFO @ 119677753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 80420682410952398078650281362425869090701135151277450489761502769609597725768 158898
UVM_INFO @ 1297660187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 4637818641585744036266179648880292554394233571864855725909938538992931129025 205
UVM_INFO @ 16794941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---