Simulation Results: aes/gcm_unmasked

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.78 %
  • code
  • 90.33 %
  • assert
  • 97.75 %
  • func
  • 63.27 %
  • block
  • 90.26 %
  • line
  • 92.46 %
  • branch
  • 82.21 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
88.24%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 117.004us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 83.302us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 52.239us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 187.082us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 503.372us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 226.171us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 88.260us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 187.082us 1 1 100.00
aes_csr_aliasing 3.000s 226.171us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 83.302us 1 1 100.00
aes_config_error 3.000s 130.711us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 83.302us 1 1 100.00
aes_config_error 3.000s 130.711us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_b2b 4.000s 122.041us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
multi_message 3 4 75.00
aes_smoke 1.000s 83.302us 1 1 100.00
aes_config_error 3.000s 130.711us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
failure_test 2 3 66.67
aes_man_cfg_err 2.000s 74.803us 1 1 100.00
aes_config_error 3.000s 130.711us 1 1 100.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 68.966us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1340.341us 1 1 100.00
reset_recovery 0 1 0.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
stress 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_sideload 3.000s 89.681us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 95.325us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 12.000s 875.027us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 52.381us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 216.569us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 216.569us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.239us 1 1 100.00
aes_csr_rw 2.000s 187.082us 1 1 100.00
aes_csr_aliasing 3.000s 226.171us 1 1 100.00
aes_same_csr_outstanding 2.000s 134.688us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 52.239us 1 1 100.00
aes_csr_rw 2.000s 187.082us 1 1 100.00
aes_csr_aliasing 3.000s 226.171us 1 1 100.00
aes_same_csr_outstanding 2.000s 134.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 134.840us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 348.654us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 1032.702us 1 1 100.00
aes_tl_intg_err 2.000s 550.767us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 550.767us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 0 1 0.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
sec_cm_main_config_sparse 3 4 75.00
aes_smoke 1.000s 83.302us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
aes_core_fi 2.000s 119.522us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 130.711us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_core_fi 2.000s 119.522us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 263.214us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 136.049us 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 156.835us 1 1 100.00
aes_sideload 3.000s 89.681us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 136.049us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 136.049us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 136.049us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 136.049us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 136.049us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 156.835us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 75.224us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 75.224us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 75.224us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 75.224us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_main_fsm_global_esc 0 1 0.00
aes_alert_reset 1956.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_ctr_fi 2.000s 74.768us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 75.224us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 75.224us 0 1 0.00
aes_control_fi 2.000s 56.156us 1 1 100.00
aes_cipher_fi 2.000s 73.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 27.152us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_alert_reset 109086012305506070830400613926179438264276059372421098035016691132780670809880 17466264
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 97665589659192196542294478619712822084787134196603205319482983342796466356031 6373
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 81016547082452769519250247599380096778300758474637079996235093921838226662931 47463
UVM_INFO @ 875026523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 40239209519932904297194924840421576799064055005462308769568648162748734903779 175
UVM_INFO @ 27151924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---