Simulation Results: alert_handler

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.18 %
  • code
  • 90.98 %
  • assert
  • 98.20 %
  • func
  • 81.37 %
  • line
  • 99.72 %
  • branch
  • 98.65 %
  • cond
  • 91.81 %
  • toggle
  • 88.90 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.170s 28.846us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.600s 285.139us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 436.420s 10976.060us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 211.570s 8386.903us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.970s 154.647us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.600s 285.139us 1 1 100.00
alert_handler_csr_aliasing 211.570s 8386.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 86.000s 4614.304us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 56.090s 1529.583us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2213.250s 344435.609us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 25.560s 434.977us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 45.730s 4992.252us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 29.990s 2681.394us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 191.680s 6335.723us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1639.050s 84467.621us 1 1 100.00
alert_handler_lpg_stub_clk 2676.210s 247879.103us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2756.110s 364263.063us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 6.070s 1524.041us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 3.190s 298.300us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.830s 20.789us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 8.060s 207.162us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 8.060s 207.162us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.170s 28.846us 1 1 100.00
alert_handler_csr_rw 7.600s 285.139us 1 1 100.00
alert_handler_csr_aliasing 211.570s 8386.903us 1 1 100.00
alert_handler_same_csr_outstanding 19.510s 1555.356us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.170s 28.846us 1 1 100.00
alert_handler_csr_rw 7.600s 285.139us 1 1 100.00
alert_handler_csr_aliasing 211.570s 8386.903us 1 1 100.00
alert_handler_same_csr_outstanding 19.510s 1555.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 231.500s 5152.330us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 231.500s 5152.330us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 231.500s 5152.330us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 231.500s 5152.330us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 468.260s 9581.814us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
alert_handler_tl_intg_err 21.190s 410.278us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 21.190s 410.278us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 231.500s 5152.330us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 14.640s 1453.976us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 25.560s 434.977us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1639.050s 84467.621us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 25.560s 434.977us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2213.250s 344435.609us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2213.250s 344435.609us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 20.470s 3644.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 110.370s 17843.434us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 101312360701862109449228313405262037890773471161065723531139777499668830473881 212
UVM_INFO @ 1524040988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 8160469079637125300652314783983176242834203048356505339724636763316606935369 129
UVM_INFO @ 17843434303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---