Simulation Results: csrng

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.55 %
  • code
  • 92.30 %
  • assert
  • 94.10 %
  • func
  • 79.25 %
  • block
  • 96.92 %
  • line
  • 97.69 %
  • branch
  • 92.43 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 48.392us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 68.852us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 1.000s 28.646us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 8.000s 160.346us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 368.071us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 27.692us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 1.000s 28.646us 1 1 100.00
csrng_csr_aliasing 6.000s 368.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 188.579us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 303.000s 26327.233us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 303.000s 26327.233us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 412.000s 10942.633us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 21.100us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 24.147us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 28.024us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 28.024us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 68.852us 1 1 100.00
csrng_csr_rw 1.000s 28.646us 1 1 100.00
csrng_csr_aliasing 6.000s 368.071us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.148us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 68.852us 1 1 100.00
csrng_csr_rw 1.000s 28.646us 1 1 100.00
csrng_csr_aliasing 6.000s 368.071us 1 1 100.00
csrng_same_csr_outstanding 3.000s 95.148us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
csrng_tl_intg_err 4.000s 239.613us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 2.908us 0 1 0.00
csrng_csr_rw 1.000s 28.646us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 188.579us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 412.000s 10942.633us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 188.579us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 412.000s 10942.633us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 188.579us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 239.613us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
csrng_sec_cm 3.000s 88.600us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 67.956us 1 1 100.00
csrng_err 2.000s 30.499us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 95556791015235818143293975630186419196291780028630184865958994160985910063599 99
UVM_INFO @ 2908193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 110202378832968343073277917507110833459551544647692794977393480995549576916926 None