Simulation Results: edn/edn0

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.06 %
  • code
  • 81.83 %
  • assert
  • 94.69 %
  • func
  • 48.67 %
  • block
  • 93.21 %
  • line
  • 96.44 %
  • branch
  • 85.49 %
  • toggle
  • 69.43 %
  • FSM
  • 75.97 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 22.346us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 23.336us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 2.000s 43.004us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 555.724us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 25.398us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 50.468us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 2.000s 43.004us 1 1 100.00
edn_csr_aliasing 2.000s 25.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 126.430us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 126.430us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 126.430us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.000s 43.437us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 51.976us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 19.170us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 22.922us 1 1 100.00
edn_disable_auto_req_mode 2.000s 35.688us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 10.000s 563.471us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 15.448us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 30.929us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 547.540us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 547.540us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.336us 1 1 100.00
edn_csr_rw 2.000s 43.004us 1 1 100.00
edn_csr_aliasing 2.000s 25.398us 1 1 100.00
edn_same_csr_outstanding 2.000s 112.715us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.000s 23.336us 1 1 100.00
edn_csr_rw 2.000s 43.004us 1 1 100.00
edn_csr_aliasing 2.000s 25.398us 1 1 100.00
edn_same_csr_outstanding 2.000s 112.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
edn_tl_intg_err 2.000s 87.038us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 26.025us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 51.976us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 51.976us 1 1 100.00
edn_sec_cm 4.000s 4834.327us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 51.976us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.000s 87.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 30.000s 3539.429us 1 1 100.00