Simulation Results: edn/edn1

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.16 %
  • code
  • 83.09 %
  • assert
  • 97.92 %
  • func
  • 80.46 %
  • line
  • 97.72 %
  • branch
  • 92.42 %
  • cond
  • 89.00 %
  • toggle
  • 95.38 %
  • FSM
  • 40.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.990s 17.298us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.960s 25.263us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 39.822us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.740s 93.922us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.060s 223.332us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 38.530us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 39.822us 1 1 100.00
edn_csr_aliasing 1.060s 223.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.340s 49.636us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.340s 49.636us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.340s 49.636us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.220s 33.978us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 41.140us 1 1 100.00
errs 1 1 100.00
edn_err 1.020s 22.421us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 20.803us 1 1 100.00
edn_disable_auto_req_mode 1.070s 75.553us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.970s 259.833us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.930s 55.230us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.980s 40.922us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.320s 23.894us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.320s 23.894us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.960s 25.263us 1 1 100.00
edn_csr_rw 0.800s 39.822us 1 1 100.00
edn_csr_aliasing 1.060s 223.332us 1 1 100.00
edn_same_csr_outstanding 1.060s 36.851us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.960s 25.263us 1 1 100.00
edn_csr_rw 0.800s 39.822us 1 1 100.00
edn_csr_aliasing 1.060s 223.332us 1 1 100.00
edn_same_csr_outstanding 1.060s 36.851us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
edn_tl_intg_err 2.210s 1515.528us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 19.602us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 41.140us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 41.140us 1 1 100.00
edn_sec_cm 4.840s 3886.288us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 41.140us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.210s 1515.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.560s 10591.763us 1 1 100.00