Simulation Results: entropy_src/rng_16bits

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 67.21 %
  • code
  • 79.53 %
  • assert
  • 74.06 %
  • func
  • 48.04 %
  • block
  • 93.90 %
  • line
  • 97.59 %
  • branch
  • 85.53 %
  • toggle
  • 50.63 %
  • FSM
  • 84.38 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 26.721us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 136.225us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 51.071us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 8.000s 426.292us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 140.391us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 41.646us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 51.071us 1 1 100.00
entropy_src_csr_aliasing 3.000s 140.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 26.721us 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
entropy_src_fw_ov 344.000s 13020.673us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 344.000s 13020.673us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 118.000s 13141.920us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
entropy_src_intr 23.000s 1544.554us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
entropy_src_functional_alerts 6.000s 347.395us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 2.000s 347.421us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 6.000s 563.209us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 34.972us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 60.201us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 125.480us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 125.480us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 136.225us 1 1 100.00
entropy_src_csr_rw 2.000s 51.071us 1 1 100.00
entropy_src_csr_aliasing 3.000s 140.391us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 31.626us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 136.225us 1 1 100.00
entropy_src_csr_rw 2.000s 51.071us 1 1 100.00
entropy_src_csr_aliasing 3.000s 140.391us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 31.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 7.000s 559.246us 1 1 100.00
entropy_src_tl_intg_err 3.000s 543.653us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
entropy_src_cfg_regwen 2.000s 36.433us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
entropy_src_fw_ov 344.000s 13020.673us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
entropy_src_sec_cm 7.000s 559.246us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
entropy_src_sec_cm 7.000s 559.246us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 53.000s 13056.156us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
entropy_src_sec_cm 7.000s 559.246us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
entropy_src_sec_cm 7.000s 559.246us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 7.000s 131.597us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 347.395us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 543.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 369.000s 13053.353us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 17.000s 2407.100us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 32209758955914719674115874156495733217082489056370609545735481822396653854670 124
UVM_INFO @ 2407099856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 77735543452645147909702024650811751762884616319829438576892224627080955367782 113
UVM_INFO @ 41646387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---