| V1 |
|
88.89% |
| V2 |
|
82.35% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 4 | 4 | 100.00 | |||
| gpio_smoke | 1.540s | 41.790us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 0.820s | 23.528us | 1 | 1 | 100.00 | |
| gpio_smoke_en_cdc_prim | 0.830s | 143.090us | 1 | 1 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.260s | 36.748us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 0.730s | 13.921us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| gpio_csr_rw | 0.710s | 20.978us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 3.130s | 1265.271us | 1 | 1 | 100.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| gpio_csr_aliasing | 2.210s | 565.735us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.450s | 30.014us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 1 | 2 | 50.00 | |||
| gpio_csr_rw | 0.710s | 20.978us | 1 | 1 | 100.00 | |
| gpio_csr_aliasing | 2.210s | 565.735us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 2 | 2 | 100.00 | |||
| gpio_random_dout_din | 1.440s | 96.915us | 1 | 1 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 0.840s | 13.880us | 1 | 1 | 100.00 | |
| out_in_regs_read_write | 1 | 1 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 0.850s | 267.900us | 1 | 1 | 100.00 | |
| gpio_interrupt_programming | 1 | 1 | 100.00 | |||
| gpio_intr_rand_pgm | 1.340s | 76.452us | 1 | 1 | 100.00 | |
| random_interrupt_trigger | 1 | 1 | 100.00 | |||
| gpio_rand_intr_trigger | 2.140s | 269.499us | 1 | 1 | 100.00 | |
| interrupt_and_noise_filter | 1 | 1 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 2.420s | 241.924us | 1 | 1 | 100.00 | |
| noise_filter_stress | 1 | 1 | 100.00 | |||
| gpio_filter_stress | 17.420s | 3700.099us | 1 | 1 | 100.00 | |
| regs_long_reads_and_writes | 1 | 1 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 2.920s | 200.333us | 1 | 1 | 100.00 | |
| full_random | 1 | 1 | 100.00 | |||
| gpio_full_random | 0.760s | 100.447us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| gpio_stress_all | 35.670s | 32545.952us | 0 | 1 | 0.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| gpio_alert_test | 0.760s | 13.135us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| gpio_intr_test | 0.820s | 18.549us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.770s | 147.005us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| gpio_tl_errors | 2.770s | 147.005us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 2 | 4 | 50.00 | |||
| gpio_csr_rw | 0.710s | 20.978us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.970s | 27.255us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 2.210s | 565.735us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 0.730s | 13.921us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 2 | 4 | 50.00 | |||
| gpio_csr_rw | 0.710s | 20.978us | 1 | 1 | 100.00 | |
| gpio_same_csr_outstanding | 0.970s | 27.255us | 0 | 1 | 0.00 | |
| gpio_csr_aliasing | 2.210s | 565.735us | 0 | 1 | 0.00 | |
| gpio_csr_hw_reset | 0.730s | 13.921us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| gpio_tl_intg_err | 1.230s | 148.642us | 1 | 1 | 100.00 | |
| gpio_sec_cm | 1.130s | 367.001us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| gpio_tl_intg_err | 1.230s | 148.642us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 1 | 1 | 100.00 | |||
| gpio_rand_straps | 0.760s | 16.623us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 7.620s | 287.690us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| gpio_inp_prd_cnt | 0.800s | 44.208us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:248) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 1 test run | |||
| gpio_stress_all | 83421637972034648286104760185879915118426791104396220038933513804959346173515 | 1877 |
UVM_INFO @ 32545951567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 1 test run | |||
| gpio_stress_all_with_rand_reset | 54074795630408390694063079015197928745928606256247531445874708644344861514770 | 81 |
UVM_INFO @ 287689958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 34486111195058795881891865572077445295865862466379401126438017714745857883814 | 76 |
UVM_INFO @ 27255325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * | 1 test run | |||
| gpio_csr_aliasing | 56502005356919744311279555137001908063463645979571499028075484015810963123228 | 78 |
UVM_INFO @ 565735354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|