Simulation Results: hmac

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.89 %
  • code
  • 95.95 %
  • assert
  • 97.17 %
  • func
  • 28.56 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.000s 31.940us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 462.528us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 131.633us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 648.157us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 154.541us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 18.879us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 131.633us 1 1 100.00
hmac_csr_aliasing 6.000s 154.541us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 49.000s 4755.055us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 34.000s 1594.883us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 205.000s 31910.403us 1 1 100.00
hmac_test_sha384_vectors 22.000s 666.882us 1 1 100.00
hmac_test_sha512_vectors 464.000s 73022.434us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 300.605us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1356.659us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 767.416us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 25.000s 2679.467us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 181.000s 5738.700us 1 1 100.00
error 1 1 100.00
hmac_error 45.000s 8873.002us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 47.000s 39477.113us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.000s 31.940us 1 1 100.00
hmac_long_msg 49.000s 4755.055us 1 1 100.00
hmac_back_pressure 34.000s 1594.883us 1 1 100.00
hmac_datapath_stress 181.000s 5738.700us 1 1 100.00
hmac_burst_wr 25.000s 2679.467us 1 1 100.00
hmac_stress_all 346.000s 174568.973us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.000s 31.940us 1 1 100.00
hmac_long_msg 49.000s 4755.055us 1 1 100.00
hmac_back_pressure 34.000s 1594.883us 1 1 100.00
hmac_datapath_stress 181.000s 5738.700us 1 1 100.00
hmac_wipe_secret 47.000s 39477.113us 1 1 100.00
hmac_test_sha256_vectors 205.000s 31910.403us 1 1 100.00
hmac_test_sha384_vectors 22.000s 666.882us 1 1 100.00
hmac_test_sha512_vectors 464.000s 73022.434us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 300.605us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1356.659us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 767.416us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.000s 31.940us 1 1 100.00
hmac_long_msg 49.000s 4755.055us 1 1 100.00
hmac_back_pressure 34.000s 1594.883us 1 1 100.00
hmac_datapath_stress 181.000s 5738.700us 1 1 100.00
hmac_burst_wr 25.000s 2679.467us 1 1 100.00
hmac_error 45.000s 8873.002us 1 1 100.00
hmac_wipe_secret 47.000s 39477.113us 1 1 100.00
hmac_test_sha256_vectors 205.000s 31910.403us 1 1 100.00
hmac_test_sha384_vectors 22.000s 666.882us 1 1 100.00
hmac_test_sha512_vectors 464.000s 73022.434us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 300.605us 1 1 100.00
hmac_test_hmac384_vectors 12.000s 1356.659us 1 1 100.00
hmac_test_hmac512_vectors 12.000s 767.416us 1 1 100.00
hmac_stress_all 346.000s 174568.973us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 346.000s 174568.973us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 49.670us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 35.815us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 57.472us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 57.472us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 462.528us 1 1 100.00
hmac_csr_rw 2.000s 131.633us 1 1 100.00
hmac_csr_aliasing 6.000s 154.541us 1 1 100.00
hmac_same_csr_outstanding 3.000s 998.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 462.528us 1 1 100.00
hmac_csr_rw 2.000s 131.633us 1 1 100.00
hmac_csr_aliasing 6.000s 154.541us 1 1 100.00
hmac_same_csr_outstanding 3.000s 998.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 465.686us 1 1 100.00
hmac_tl_intg_err 2.000s 50.994us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.000s 50.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.000s 31.940us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 60.012us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 93.000s 6799.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 349.408us 1 1 100.00