Simulation Results

Simulation Results: i2c

06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.93 %

code
86.38 %

assert
96.19 %

func
81.22 %

block
96.14 %

line
95.60 %

branch
93.09 %

toggle
72.64 %

FSM
84.17 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	34.000s	1136.943us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	20.000s	1095.212us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	82.591us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	16.970us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	5.000s	2223.570us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	44.460us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	43.003us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	16.970us	1	1	100.00
	i2c_csr_aliasing	2.000s	44.460us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	15.960us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1.000s	6.651us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	288.000s	8559.555us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	27.892us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	3002.000s	3509.345us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1278.000s	9573.669us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	80.180us	1	1	100.00
	i2c_host_fifo_fmt_empty	15.000s	246.000us	1	1	100.00
	i2c_host_fifo_reset_rx	3.000s	108.818us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	137.000s	3150.537us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.000s	811.933us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	2.000s	400.237us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	405.786us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	518.699us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	18.000s	2675.255us	1	1	100.00
	i2c_target_intr_smoke	5.000s	666.032us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	162.179us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	848.063us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	5.000s	15898.345us	1	1	100.00
	i2c_target_stress_rd	18.000s	2675.255us	1	1	100.00
	i2c_target_intr_stress_wr	23.000s	7414.423us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	7.000s	4791.360us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	4.000s	2801.894us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	718.522us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	3.000s	259.607us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	1879.347us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	303.286us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	288.000s	8559.555us	1	1	100.00
	i2c_host_perf_precise	14.000s	2531.199us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.000s	811.933us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	7.000s	771.927us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	642.096us	1	1	100.00
	i2c_target_nack_acqfull_addr	3.000s	856.764us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	312.300us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	15.000s	591.111us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	3.000s	4924.440us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	3.000s	15.464us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	18.625us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	46.524us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	46.524us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	82.591us	1	1	100.00
	i2c_csr_rw	1.000s	16.970us	1	1	100.00
	i2c_csr_aliasing	2.000s	44.460us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	80.083us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	82.591us	1	1	100.00
	i2c_csr_rw	1.000s	16.970us	1	1	100.00
	i2c_csr_aliasing	2.000s	44.460us	1	1	100.00
	i2c_same_csr_outstanding	1.000s	80.083us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	63.469us	1	1	100.00
	i2c_sec_cm	1.000s	80.518us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	63.469us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.000s	130.859us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	1619.210us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	4.000s	1810.064us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	90336366807034893246388979311832393508095658683342582850316794072395133327427	89	UVM_INFO @ 15959690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	114897408281336635941682088857289797307911159218705333693018058622094025769801	95	UVM_INFO @ 6650909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	104454260937784672950291923721982533139131949156346253700095545194586687578971	93	UVM_INFO @ 130859449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	57700890434663981365891673215164995233851786476379043401135076421014895814242	92	UVM_INFO @ 1810063545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	44073006405946782186713165958267125138938175944050464087733467313723426616809	93	UVM_INFO @ 405786322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/i2c-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_i2c_/rtl/i2c_fifos.sv,320): Assertion TxWriteStableBeforeHandshake_A has failed (* cycles, starting * PS)				1 test run
	i2c_target_unexp_stop	2768144464228248612785185249420339751124442833419987754604366249160305853928	89	UVM_ERROR @ 1619209728 ps: (i2c_fifos.sv:320) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 1619209728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_target_stress_all	85616609828316159602741676051856778587454788414028236014458403224066012502942	None
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	76939375476732675581773421088334062453938957122618397590158872629367194392871	94	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @17105