| V1 |
|
100.00% |
| V2 |
|
68.97% |
| V2S |
|
87.50% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| kmac_smoke | 9.760s | 363.143us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| kmac_csr_hw_reset | 0.950s | 63.787us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| kmac_csr_rw | 1.170s | 26.589us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| kmac_csr_bit_bash | 8.740s | 924.343us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| kmac_csr_aliasing | 3.980s | 502.676us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| kmac_csr_mem_rw_with_rand_reset | 1.330s | 162.840us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| kmac_csr_rw | 1.170s | 26.589us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 3.980s | 502.676us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| kmac_mem_walk | 0.840s | 31.725us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| kmac_mem_partial_access | 1.380s | 41.331us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| long_msg_and_output | 1 | 1 | 100.00 | |||
| kmac_long_msg_and_output | 3802.620s | 450869.143us | 1 | 1 | 100.00 | |
| burst_write | 1 | 1 | 100.00 | |||
| kmac_burst_write | 1020.320s | 68120.547us | 1 | 1 | 100.00 | |
| test_vectors | 8 | 8 | 100.00 | |||
| kmac_test_vectors_sha3_224 | 2400.650s | 115266.680us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_256 | 34.660s | 67186.502us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_384 | 29.790s | 22803.386us | 1 | 1 | 100.00 | |
| kmac_test_vectors_sha3_512 | 15.870s | 1443.110us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_128 | 2767.790s | 121732.272us | 1 | 1 | 100.00 | |
| kmac_test_vectors_shake_256 | 96.180s | 13836.779us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac | 3.700s | 1047.313us | 1 | 1 | 100.00 | |
| kmac_test_vectors_kmac_xof | 2.260s | 104.482us | 1 | 1 | 100.00 | |
| sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 414.320s | 99427.987us | 1 | 1 | 100.00 | |
| app | 0 | 1 | 0.00 | |||
| kmac_app | 3.200s | 277.693us | 0 | 1 | 0.00 | |
| app_with_partial_data | 0 | 1 | 0.00 | |||
| kmac_app_with_partial_data | 2.000s | 683.121us | 0 | 1 | 0.00 | |
| entropy_refresh | 0 | 1 | 0.00 | |||
| kmac_entropy_refresh | 1.680s | 162.770us | 0 | 1 | 0.00 | |
| error | 0 | 1 | 0.00 | |||
| kmac_error | 13.830s | 3152.923us | 0 | 1 | 0.00 | |
| key_error | 0 | 1 | 0.00 | |||
| kmac_key_error | 0.900s | 13.106us | 0 | 1 | 0.00 | |
| sideload_invalid | 0 | 1 | 0.00 | |||
| kmac_sideload_invalid | 1.620s | 121.915us | 0 | 1 | 0.00 | |
| edn_timeout_error | 0 | 1 | 0.00 | |||
| kmac_edn_timeout_error | 14.490s | 3619.941us | 0 | 1 | 0.00 | |
| entropy_mode_error | 1 | 1 | 100.00 | |||
| kmac_entropy_mode_error | 1.390s | 388.147us | 1 | 1 | 100.00 | |
| entropy_ready_error | 0 | 1 | 0.00 | |||
| kmac_entropy_ready_error | 1.010s | 130.689us | 0 | 1 | 0.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.430s | 84.623us | 1 | 1 | 100.00 | |
| stress_all | 0 | 1 | 0.00 | |||
| kmac_stress_all | 60.420s | 3966.220us | 0 | 1 | 0.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| kmac_intr_test | 0.760s | 33.751us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| kmac_alert_test | 0.960s | 44.979us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 4.240s | 198.769us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| kmac_tl_errors | 4.240s | 198.769us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.950s | 63.787us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 1.170s | 26.589us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 3.980s | 502.676us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 1.870s | 40.789us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| kmac_csr_hw_reset | 0.950s | 63.787us | 1 | 1 | 100.00 | |
| kmac_csr_rw | 1.170s | 26.589us | 1 | 1 | 100.00 | |
| kmac_csr_aliasing | 3.980s | 502.676us | 1 | 1 | 100.00 | |
| kmac_same_csr_outstanding | 1.870s | 40.789us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.330s | 47.404us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.330s | 47.404us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.330s | 47.404us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.330s | 47.404us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors_with_csr_rw | 4.100s | 258.426us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| kmac_sec_cm | 41.950s | 35672.705us | 1 | 1 | 100.00 | |
| kmac_tl_intg_err | 3.040s | 155.499us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| kmac_tl_intg_err | 3.040s | 155.499us | 1 | 1 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.430s | 84.623us | 1 | 1 | 100.00 | |
| sec_cm_sw_key_key_masking | 1 | 1 | 100.00 | |||
| kmac_smoke | 9.760s | 363.143us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| kmac_sideload | 414.320s | 99427.987us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_shadow | 1 | 1 | 100.00 | |||
| kmac_shadow_reg_errors | 1.330s | 47.404us | 1 | 1 | 100.00 | |
| sec_cm_fsm_sparse | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 41.950s | 35672.705us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 41.950s | 35672.705us | 1 | 1 | 100.00 | |
| sec_cm_packer_ctr_redun | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 41.950s | 35672.705us | 1 | 1 | 100.00 | |
| sec_cm_cfg_shadowed_config_regwen | 1 | 1 | 100.00 | |||
| kmac_smoke | 9.760s | 363.143us | 1 | 1 | 100.00 | |
| sec_cm_fsm_global_esc | 1 | 1 | 100.00 | |||
| kmac_lc_escalation | 1.430s | 84.623us | 1 | 1 | 100.00 | |
| sec_cm_fsm_local_esc | 1 | 1 | 100.00 | |||
| kmac_sec_cm | 41.950s | 35672.705us | 1 | 1 | 100.00 | |
| sec_cm_absorbed_ctrl_mubi | 0 | 1 | 0.00 | |||
| kmac_mubi | 14.710s | 806.536us | 0 | 1 | 0.00 | |
| sec_cm_sw_cmd_ctrl_sparse | 1 | 1 | 100.00 | |||
| kmac_smoke | 9.760s | 363.143us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| kmac_stress_all_with_rand_reset | 65.360s | 11649.007us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] | 6 test runs | |||
| kmac_sideload_invalid | 33035900627238384170245069309647116504893567103646989576724014265871988217153 | 79 |
UVM_INFO @ 121914965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app | 60158068221147023219271180114167116534658184157871621645735047848405144806936 | 78 |
UVM_INFO @ 277693375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_app_with_partial_data | 31710379241586988551939505857582378782249569716541991988842226800192313483888 | 77 |
UVM_INFO @ 683121219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_refresh | 84096058420487874631637204252713095422599593096685725885214427874639472169174 | 77 |
UVM_INFO @ 162769910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_error | 21832467440675616760594424170826341540410180443504655801237817069245455719650 | 82 |
UVM_INFO @ 3152923050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all_with_rand_reset | 84025178789432194200190830261398747594193944768830352814780555623925362199639 | 207 |
UVM_INFO @ 11649006982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' | 3 test runs | |||
| kmac_key_error | 23567763563600197862554807074030205808014095134597898809639352018174986861616 | 78 |
UVM_ERROR @ 13105610 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 13105610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_edn_timeout_error | 107820884890813751098198685131538483664711107132055256681717373527243110626227 | 87 |
UVM_ERROR @ 3619941308 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 3619941308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_entropy_ready_error | 95341590756172114867530249863353897135605802778312843826464771790261522493855 | 78 |
UVM_ERROR @ 130689267 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 130689267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) | 2 test runs | |||
| kmac_mubi | 69843359003878064480517869980344161171148505613843500588817929520610982908481 | 83 |
UVM_INFO @ 806536287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| kmac_stress_all | 100964184990269989259473441166625600856481888457591661430335616854422362475913 | 117 |
UVM_INFO @ 3966219734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|