Simulation Results: kmac/unmasked

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.34 %
  • code
  • 66.59 %
  • assert
  • 96.50 %
  • func
  • 74.93 %
  • line
  • 92.81 %
  • branch
  • 87.05 %
  • cond
  • 84.66 %
  • toggle
  • 27.54 %
  • FSM
  • 40.88 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 47.130s 4065.703us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.020s 61.211us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.200s 27.972us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.390s 216.985us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 7.220s 2232.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.730s 29.585us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.200s 27.972us 1 1 100.00
kmac_csr_aliasing 7.220s 2232.255us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.840s 23.114us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.920s 214.756us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2177.710s 96864.968us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 208.950s 9641.811us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1365.290s 107114.005us 1 1 100.00
kmac_test_vectors_sha3_256 2086.860s 214685.248us 1 1 100.00
kmac_test_vectors_sha3_384 26.930s 7541.045us 1 1 100.00
kmac_test_vectors_sha3_512 15.540s 1130.482us 1 1 100.00
kmac_test_vectors_shake_128 150.290s 67927.256us 1 1 100.00
kmac_test_vectors_shake_256 2035.900s 111510.801us 1 1 100.00
kmac_test_vectors_kmac 2.340s 277.761us 1 1 100.00
kmac_test_vectors_kmac_xof 2.010s 81.662us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 186.150s 13181.166us 1 1 100.00
app 0 1 0.00
kmac_app 6.320s 605.507us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.430s 231.428us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 5.870s 461.373us 0 1 0.00
error 0 1 0.00
kmac_error 35.180s 4551.347us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 0.850s 114.995us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.960s 66.253us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 6.320s 316.743us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 15.440s 1303.802us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.970s 63.871us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.240s 64.843us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 3.310s 1039.030us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.930s 17.218us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.870s 16.483us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.640s 55.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.640s 55.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.020s 61.211us 1 1 100.00
kmac_csr_rw 1.200s 27.972us 1 1 100.00
kmac_csr_aliasing 7.220s 2232.255us 1 1 100.00
kmac_same_csr_outstanding 1.540s 61.260us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.020s 61.211us 1 1 100.00
kmac_csr_rw 1.200s 27.972us 1 1 100.00
kmac_csr_aliasing 7.220s 2232.255us 1 1 100.00
kmac_same_csr_outstanding 1.540s 61.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 213.925us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.430s 213.925us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.430s 213.925us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.430s 213.925us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.240s 239.519us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 30.940s 3534.268us 1 1 100.00
kmac_tl_intg_err 2.590s 131.903us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.590s 131.903us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.240s 64.843us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 47.130s 4065.703us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 186.150s 13181.166us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.430s 213.925us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 30.940s 3534.268us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 30.940s 3534.268us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 30.940s 3534.268us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 47.130s 4065.703us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.240s 64.843us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 30.940s 3534.268us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 7.470s 156.494us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 47.130s 4065.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 5.590s 942.087us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_app 36566184992335636369003928877678524573409188762856251350693670630555240429753 80
UVM_INFO @ 605507453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 94175948560513921081032235146182115230802261125450634641969951253546830826211 78
UVM_INFO @ 231428116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 39421723346497564341241116715659310173314372472644558926297988715591208011210 79
UVM_INFO @ 461373157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 98688950548592962798561230999379489652359625786042898503893192049298685246727 98
UVM_INFO @ 4551347038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 68856596483589952415408600356838622318029246109808491267781351235187798471437 77
UVM_INFO @ 63870604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 78278124179895686256080514089596631192316253400485450454798950607890703177251 86
UVM_INFO @ 1039029689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 45888912825281546280922918406862800258585499802010673449314990162201929382096 97
UVM_INFO @ 942086858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 107933002670447864685497716598251603891606850088398174404682920863310790480874 79
UVM_ERROR @ 66252764 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 66252764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 22053317435030506988230835792980934341767376320944682651011108586285399226306 78
UVM_ERROR @ 114995220 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 114995220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 106433905012907708891514340011921900283592183109293392710232824166265928212902 82
UVM_INFO @ 156494437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---