Simulation Results: lc_ctrl/volatile_unlock_disabled

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.99 %
  • code
  • 92.94 %
  • assert
  • 96.40 %
  • func
  • 86.62 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 87.86 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 57.668us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 46.447us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.480us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 381.652us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 7.000s 80.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 22.579us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 27.480us 1 1 100.00
lc_ctrl_csr_aliasing 7.000s 80.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.000s 65.094us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 1312.224us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 42.336us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 198.312us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.000s 893.166us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_prog_failure 2.000s 198.312us 1 1 100.00
lc_ctrl_errors 5.000s 893.166us 1 1 100.00
lc_ctrl_security_escalation 7.000s 1688.187us 1 1 100.00
lc_ctrl_jtag_state_failure 31.000s 8711.812us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 2244.350us 1 1 100.00
lc_ctrl_jtag_errors 27.000s 1579.605us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.000s 386.686us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 490.481us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 2244.350us 1 1 100.00
lc_ctrl_jtag_errors 27.000s 1579.605us 1 1 100.00
lc_ctrl_jtag_access 4.000s 177.183us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.000s 3883.994us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 66.350us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 46.375us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.000s 609.550us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 1204.401us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 103.701us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 188.883us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 37.168us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 969.099us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 25.547us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 49.000s 7314.346us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 93.150us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 134.258us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.000s 134.258us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 46.447us 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.480us 1 1 100.00
lc_ctrl_csr_aliasing 7.000s 80.817us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 137.585us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 46.447us 1 1 100.00
lc_ctrl_csr_rw 2.000s 27.480us 1 1 100.00
lc_ctrl_csr_aliasing 7.000s 80.817us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 137.585us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 422.050us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 422.050us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.000s 1312.224us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.000s 406.402us 1 1 100.00
lc_ctrl_sec_cm 2.000s 721.965us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.000s 1688.187us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.000s 65.094us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.000s 490.481us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 425.015us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 425.015us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 414.793us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 393.994us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 393.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 66.000s 4030.218us 1 1 100.00