Simulation Results: lc_ctrl/volatile_unlock_enabled

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.05 %
  • code
  • 93.86 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 97.02 %
  • line
  • 97.60 %
  • branch
  • 92.45 %
  • toggle
  • 87.78 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 49.856us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 205.271us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 41.374us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 593.702us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.114us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 32.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 41.374us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 8.000s 88.311us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 295.850us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 22.562us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.000s 160.747us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.000s 1234.488us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_prog_failure 1.000s 160.747us 1 1 100.00
lc_ctrl_errors 7.000s 1234.488us 1 1 100.00
lc_ctrl_security_escalation 4.000s 314.495us 1 1 100.00
lc_ctrl_jtag_state_failure 15.000s 1706.442us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 448.689us 1 1 100.00
lc_ctrl_jtag_errors 30.000s 7686.390us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.000s 1955.725us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 5942.554us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 448.689us 1 1 100.00
lc_ctrl_jtag_errors 30.000s 7686.390us 1 1 100.00
lc_ctrl_jtag_access 4.000s 198.015us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 17.000s 2592.035us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 438.512us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 194.060us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.000s 462.566us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 1560.295us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 15.762us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 180.980us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 39.359us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 1504.470us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.687us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 34.000s 33774.633us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 76.439us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 52.023us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.000s 52.023us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 205.271us 1 1 100.00
lc_ctrl_csr_rw 2.000s 41.374us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.114us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 205.271us 1 1 100.00
lc_ctrl_csr_rw 2.000s 41.374us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 26.114us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 30.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 122.506us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 122.506us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.000s 295.850us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.000s 1085.052us 1 1 100.00
lc_ctrl_sec_cm 4.000s 247.294us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.000s 314.495us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 8.000s 88.311us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.000s 5942.554us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 426.043us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.000s 426.043us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 471.143us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 692.490us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 692.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 8.000s 924.507us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 40480266128254792594341686317707367983614673249102124126108467172680767595567 2468
UVM_INFO @ 924506779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---