Simulation Results: mbx

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.99 %
  • code
  • 88.14 %
  • assert
  • 97.34 %
  • func
  • 75.49 %
  • block
  • 95.99 %
  • line
  • 95.47 %
  • branch
  • 89.37 %
  • toggle
  • 79.59 %
Validation stages
V1
83.33%
V2
81.82%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 25.000s 2454.406us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 16.699us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 127.036us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 343.538us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 21.079us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 19.640us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 127.036us 1 1 100.00
mbx_csr_aliasing 1.000s 21.079us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 4.000s 451.595us 0 1 0.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 105.000s 6476.129us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 48.000s 11235.241us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 14.000s 1114.798us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 15.943us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 39.909us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 5.383us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 5.383us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 16.699us 1 1 100.00
mbx_csr_rw 2.000s 127.036us 1 1 100.00
mbx_csr_aliasing 1.000s 21.079us 1 1 100.00
mbx_same_csr_outstanding 2.000s 24.909us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 16.699us 1 1 100.00
mbx_csr_rw 2.000s 127.036us 1 1 100.00
mbx_csr_aliasing 1.000s 21.079us 1 1 100.00
mbx_same_csr_outstanding 2.000s 24.909us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 851.473us 1 1 100.00
mbx_sec_cm 1.000s 11.271us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 45943062931062228853082455614203623837203552371345856690899286033811473380937 85
TL item was: req: (cip_tl_seq_item@17712) { a_addr: 'h5c70a454 a_data: 'h5e80d42f a_mask: 'h9 a_size: 'h2 a_param: 'h0 a_source: 'hec a_opcode: 'h1 a_user: 'h24d6c d_param: 'h0 d_source: 'hec d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 5382745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 37397694252959228236952534526856077956038031599327317428841083009984768144279 92
TL item was: req: (cip_tl_seq_item@22078) { a_addr: 'h53c19e54 a_data: 'haf3743a3 a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'h84 a_opcode: 'h1 a_user: 'h277d4 d_param: 'h0 d_source: 'h84 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 19640400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register 1 test run
mbx_stress 88922583651224577914374227956447460982919369457506172756705812703786990556795 194
UVM_INFO @ 451594792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---