Simulation Results: otbn

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.71 %
  • code
  • 80.97 %
  • assert
  • 87.68 %
  • func
  • 94.49 %
  • block
  • 97.69 %
  • line
  • 97.89 %
  • branch
  • 81.62 %
  • toggle
  • 81.00 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 123.936us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 21.710us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 31.432us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 51.190us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 51.123us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 28.531us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 31.432us 1 1 100.00
otbn_csr_aliasing 4.000s 51.123us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 104.000s 11402.092us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 31.000s 2091.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 27.000s 74.013us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 69.000s 221.161us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 55.000s 528.033us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 58.000s 295.554us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 107.359us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 21.449us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 18.000s 130.072us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 23.419us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 161.704us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 63.943us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 63.943us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 21.710us 1 1 100.00
otbn_csr_rw 3.000s 31.432us 1 1 100.00
otbn_csr_aliasing 4.000s 51.123us 1 1 100.00
otbn_same_csr_outstanding 3.000s 343.869us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 21.710us 1 1 100.00
otbn_csr_rw 3.000s 31.432us 1 1 100.00
otbn_csr_aliasing 4.000s 51.123us 1 1 100.00
otbn_same_csr_outstanding 3.000s 343.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 28.218us 1 1 100.00
otbn_dmem_err 11.000s 36.908us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 10.000s 211.566us 1 1 100.00
otbn_controller_ispr_rdata_err 19.000s 161.001us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 203.045us 1 1 100.00
otbn_urnd_err 8.000s 18.289us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 78.803us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 15.594us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 57.255us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
otbn_tl_intg_err 30.000s 182.438us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 5.000s 4.189us 0 1 0.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 123.936us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 11.000s 36.908us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 28.218us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 30.000s 182.438us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 107.359us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 28.218us 1 1 100.00
otbn_dmem_err 11.000s 36.908us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 21.449us 1 1 100.00
otbn_illegal_mem_acc 9.000s 78.803us 1 1 100.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 28.218us 1 1 100.00
otbn_dmem_err 11.000s 36.908us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 21.449us 1 1 100.00
otbn_illegal_mem_acc 9.000s 78.803us 1 1 100.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 107.359us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 10.000s 28.218us 1 1 100.00
otbn_dmem_err 11.000s 36.908us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 21.449us 1 1 100.00
otbn_illegal_mem_acc 9.000s 78.803us 1 1 100.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 7.000s 17.040us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 93.846us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 19.000s 204.309us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 19.000s 204.309us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 17.859us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 57.404us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 35.769us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 12.000s 35.769us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 79.089us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 55.000s 528.033us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 15.000s 35.516us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 41.265us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 4.000s 2.616us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 70.000s 294.412us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 10.000s 40.388us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 71233766890971974478711097163172361175330408586986124229919776399769957507622 236
UVM_INFO @ 294411962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 21174760754265610765510708595862494255735619630225808865239961707070761538217 86
UVM_INFO @ 4189348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 105281917692810321617076692422981301953137340017060982103570037157283090098316 85
UVM_ERROR @ 2616469 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 2616469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---