Simulation Results: otp_ctrl

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.25 %
  • code
  • 71.84 %
  • assert
  • 91.67 %
  • func
  • 53.25 %
  • line
  • 87.28 %
  • branch
  • 82.67 %
  • cond
  • 85.29 %
  • toggle
  • 66.96 %
  • FSM
  • 37.02 %
Validation stages
V1
100.00%
V2
75.00%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 3.000s 835.275us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.040s 103.949us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.710s 86.652us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.380s 594.989us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.800s 522.514us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.560s 124.190us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.710s 86.652us 1 1 100.00
otp_ctrl_csr_aliasing 6.800s 522.514us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.600s 82.210us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.670s 151.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 130.750s 15369.418us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.720s 554.705us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 11.850s 5414.092us 0 1 0.00
otp_ctrl_check_fail 5.610s 1093.805us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.540s 170.223us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 7.370s 1387.424us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.860s 815.812us 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 61.310s 42883.955us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 19.230s 1348.374us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 4.600s 268.938us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 5.970s 3270.395us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.420s 90.394us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.170s 866.362us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.710s 777.592us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.710s 777.592us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 103.949us 1 1 100.00
otp_ctrl_csr_rw 1.710s 86.652us 1 1 100.00
otp_ctrl_csr_aliasing 6.800s 522.514us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.590s 190.054us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.040s 103.949us 1 1 100.00
otp_ctrl_csr_rw 1.710s 86.652us 1 1 100.00
otp_ctrl_csr_aliasing 6.800s 522.514us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.590s 190.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 22.400s 1566.220us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 22.400s 1566.220us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_macro_errs 19.230s 1348.374us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_macro_errs 19.230s 1348.374us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 10.260s 1237.893us 1 1 100.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.720s 554.705us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 5.610s 1093.805us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 13.460s 911.765us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 304.550s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.540s 170.223us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.060s 265.622us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 19.230s 1348.374us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 102.570s 62978.176us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 33.100s 10776.525us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 69953891746640477235825803309977298993026098901353645663837561761016388750969 12746
UVM_INFO @ 5414092240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 105250027247402206623027349411141683534968238937880612625805910937136547428653 17001
UVM_INFO @ 911765245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95909850935770913957800127205994755890847801610649079597636669725819299296221 2723
UVM_INFO @ 1093805032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 68847562678940510884853085144905617658177953774080922260789743333917758306237 4200
UVM_INFO @ 3270395281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 53884818395309413552470472451521137443803721162808740658190107601570811345924 112789
UVM_INFO @ 15369418304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 48919392297508492737133035076256885929031415075301991941733134075877549532652 89
UVM_INFO @ 62978176171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 106691035286523828204487384678951182665769460819947094600363081573346469412243 619
UVM_INFO @ 10776525213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 76493156214215647407278455567516236469483580519333645247168117269680701515921 2367
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---