Simulation Results: rom_ctrl/32kb

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.31 %
  • code
  • 91.73 %
  • assert
  • 97.67 %
  • func
  • 87.53 %
  • block
  • 95.04 %
  • line
  • 95.70 %
  • branch
  • 91.40 %
  • toggle
  • 84.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 184.692us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.000s 621.092us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.000s 174.210us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 579.339us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 2627.484us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 169.546us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.000s 174.210us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 2627.484us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 191.859us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 290.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 84.368us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.000s 1043.283us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 299.333us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.000s 125.567us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 188.057us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 188.057us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 621.092us 1 1 100.00
rom_ctrl_csr_rw 4.000s 174.210us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 2627.484us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 166.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 3.000s 621.092us 1 1 100.00
rom_ctrl_csr_rw 4.000s 174.210us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 2627.484us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 166.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 578.004us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
rom_ctrl_tl_intg_err 15.000s 3248.887us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 184.692us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 184.692us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 184.692us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 15.000s 3248.887us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
rom_ctrl_kmac_err_chk 5.000s 299.333us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 30.000s 2160.907us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 578.004us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 53.000s 1261.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 8.000s 259.402us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 55304449650701328063756915104755168633617286464208414971737531481226323890905 88
UVM_INFO @ 84367604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 83710734080327763418493767615780057709093966155185712605688879669758684555120 90
UVM_INFO @ 259402383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---