Simulation Results: rom_ctrl/64kb

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.80 %
  • code
  • 93.48 %
  • assert
  • 96.80 %
  • func
  • 94.12 %
  • block
  • 95.74 %
  • line
  • 96.03 %
  • branch
  • 93.28 %
  • toggle
  • 84.62 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 5.000s 416.047us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 705.010us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.000s 1804.329us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.000s 1023.218us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 287.612us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 1109.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.000s 1804.329us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 287.612us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 5.000s 297.255us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 543.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 5.000s 689.069us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.000s 2059.186us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 1078.316us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.000s 1491.484us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 640.561us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 640.561us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 705.010us 1 1 100.00
rom_ctrl_csr_rw 5.000s 1804.329us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 287.612us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 727.676us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 705.010us 1 1 100.00
rom_ctrl_csr_rw 5.000s 1804.329us 1 1 100.00
rom_ctrl_csr_aliasing 5.000s 287.612us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 727.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.000s 1472.970us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
rom_ctrl_tl_intg_err 46.000s 490.861us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 5.000s 416.047us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 5.000s 416.047us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 5.000s 416.047us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 46.000s 490.861us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
rom_ctrl_kmac_err_chk 9.000s 1078.316us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 71.000s 19145.890us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 16.000s 1472.970us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.000s 2596.196us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 12.000s 402.229us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 104677467788887724139536749920506439598899723284128589439766239972399610627468 88
UVM_INFO @ 689069067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 12397324223916727196242922445966532690204936850024870473381597459070731115832 93
UVM_INFO @ 402229364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---