Simulation Results: rstmgr

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.56 %
  • code
  • 99.27 %
  • assert
  • 98.53 %
  • func
  • 91.87 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.540s 72.753us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.630s 92.525us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.780s 81.633us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.440s 44.065us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.870s 96.219us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00
rstmgr_csr_aliasing 1.440s 44.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.790s 185.681us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.970s 37.368us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.840s 42.925us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 7.310s 864.764us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 7.310s 864.764us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 7.310s 864.764us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 7.310s 864.764us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 1.590s 183.682us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.190s 38.275us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.530s 67.827us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.530s 67.827us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.630s 92.525us 1 1 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00
rstmgr_csr_aliasing 1.440s 44.065us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 73.319us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.630s 92.525us 1 1 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00
rstmgr_csr_aliasing 1.440s 44.065us 1 1 100.00
rstmgr_same_csr_outstanding 1.160s 73.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 32.100s 7136.170us 1 1 100.00
rstmgr_tl_intg_err 2.530s 346.329us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 32.100s 7136.170us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 32.100s 7136.170us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.530s 346.329us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.100s 59.693us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.200s 484.063us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.100s 290.995us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 32.100s 7136.170us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.980s 36.922us 1 1 100.00