Simulation Results

Simulation Results: rv_dm/use_dmi_interface

06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
91.02 %

code
81.97 %

assert
96.66 %

func
94.42 %

block
92.90 %

line
93.46 %

branch
80.73 %

toggle
73.31 %

FSM
80.36 %

Validation stages

V1		96.30%
V2		73.91%
V2S		100.00%
V3		0.00%
unmapped		0.00%

26/27 passed

96.30 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	rv_dm_smoke	38.000s	3367.504us	1	1	100.00
jtag_dtm_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dtm_csr_hw_reset	31.000s	307.153us	1	1	100.00
jtag_dtm_csr_rw				1	1	100.00
	rv_dm_jtag_dtm_csr_rw	31.000s	145.249us	1	1	100.00
jtag_dtm_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dtm_csr_bit_bash	36.000s	4618.121us	1	1	100.00
jtag_dtm_csr_aliasing				1	1	100.00
	rv_dm_jtag_dtm_csr_aliasing	30.000s	274.132us	1	1	100.00
jtag_dmi_csr_hw_reset				1	1	100.00
	rv_dm_jtag_dmi_csr_hw_reset	35.000s	2521.724us	1	1	100.00
jtag_dmi_csr_rw				1	1	100.00
	rv_dm_jtag_dmi_csr_rw	31.000s	2361.203us	1	1	100.00
jtag_dmi_csr_bit_bash				1	1	100.00
	rv_dm_jtag_dmi_csr_bit_bash	46.000s	12778.201us	1	1	100.00
jtag_dmi_csr_aliasing				1	1	100.00
	rv_dm_jtag_dmi_csr_aliasing	65.000s	31150.615us	1	1	100.00
jtag_dmi_cmderr_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	783.065us	1	1	100.00
jtag_dmi_cmderr_not_supported				1	1	100.00
	rv_dm_cmderr_not_supported	33.000s	607.172us	1	1	100.00
cmderr_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	132.145us	1	1	100.00
mem_tl_access_resuming				0	1	0.00
	rv_dm_mem_tl_access_resuming	31.000s	227.061us	0	1	0.00
mem_tl_access_halted				1	1	100.00
	rv_dm_mem_tl_access_halted	30.000s	236.186us	1	1	100.00
cmderr_halt_resume				1	1	100.00
	rv_dm_cmderr_halt_resume	34.000s	156.202us	1	1	100.00
dataaddr_rw_access				1	1	100.00
	rv_dm_dataaddr_rw_access	34.000s	109.526us	1	1	100.00
halt_resume				1	1	100.00
	rv_dm_halt_resume_whereto	30.000s	424.150us	1	1	100.00
progbuf_busy				1	1	100.00
	rv_dm_cmderr_busy	32.000s	783.065us	1	1	100.00
abstractcmd_status				1	1	100.00
	rv_dm_abstractcmd_status	35.000s	122.700us	1	1	100.00
progbuf_read_write_execute				1	1	100.00
	rv_dm_progbuf_read_write_execute	32.000s	811.888us	1	1	100.00
progbuf_exception				1	1	100.00
	rv_dm_cmderr_exception	33.000s	132.145us	1	1	100.00
rom_read_access				1	1	100.00
	rv_dm_rom_read_access	31.000s	38.308us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	31.000s	369.187us	1	1	100.00
csr_rw				1	1	100.00
	rv_dm_csr_rw	31.000s	138.058us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	73.000s	18917.981us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	58.000s	1434.782us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_dm_csr_mem_rw_with_rand_reset	32.000s	298.388us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_dm_csr_aliasing	58.000s	1434.782us	1	1	100.00
	rv_dm_csr_rw	31.000s	138.058us	1	1	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	30.000s	60.083us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	30.000s	39.547us	1	1	100.00

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				1	1	100.00
	rv_dm_smoke	38.000s	3367.504us	1	1	100.00
jtag_dtm_hard_reset				1	1	100.00
	rv_dm_jtag_dtm_hard_reset	30.000s	195.256us	1	1	100.00
jtag_dtm_idle_hint				1	1	100.00
	rv_dm_jtag_dtm_idle_hint	30.000s	219.359us	1	1	100.00
jtag_dmi_failed_op				1	1	100.00
	rv_dm_dmi_failed_op	30.000s	102.553us	1	1	100.00
jtag_dmi_dm_inactive				1	1	100.00
	rv_dm_jtag_dmi_dm_inactive	32.000s	742.779us	1	1	100.00
sba				0	2	0.00
	rv_dm_sba_tl_access	37.000s	3435.926us	0	1	0.00
	rv_dm_delayed_resp_sba_tl_access	30.000s	74.509us	0	1	0.00
bad_sba				0	1	0.00
	rv_dm_bad_sba_tl_access	37.000s	4570.790us	0	1	0.00
sba_autoincrement				1	1	100.00
	rv_dm_autoincr_sba_tl_access	41.000s	10821.710us	1	1	100.00
jtag_dmi_debug_disabled				0	1	0.00
	rv_dm_jtag_dmi_debug_disabled	31.000s	124.447us	0	1	0.00
sba_debug_disabled				1	1	100.00
	rv_dm_sba_debug_disabled	31.000s	829.283us	1	1	100.00
ndmreset_req				1	1	100.00
	rv_dm_ndmreset_req	30.000s	168.946us	1	1	100.00
hart_unavail				0	1	0.00
	rv_dm_hart_unavail	31.000s	229.164us	0	1	0.00
tap_ctrl_transitions				2	2	100.00
	rv_dm_tap_fsm	43.000s	9940.825us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	55.000s	6598.170us	1	1	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	35.000s	87.774us	1	1	100.00
stress_all				0	1	0.00
	rv_dm_stress_all	30.000s	826.566us	0	1	0.00
alert_test				1	1	100.00
	rv_dm_alert_test	32.000s	42.145us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_dm_tl_errors	32.000s	340.854us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_dm_tl_errors	32.000s	340.854us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_dm_csr_aliasing	58.000s	1434.782us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	369.187us	1	1	100.00
	rv_dm_csr_rw	31.000s	138.058us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1603.873us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_dm_csr_aliasing	58.000s	1434.782us	1	1	100.00
	rv_dm_csr_hw_reset	31.000s	369.187us	1	1	100.00
	rv_dm_csr_rw	31.000s	138.058us	1	1	100.00
	rv_dm_same_csr_outstanding	33.000s	1603.873us	1	1	100.00

V2S

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_dm_sec_cm	29.000s	876.751us	1	1	100.00
	rv_dm_tl_intg_err	40.000s	9506.941us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_dm_tl_intg_err	40.000s	9506.941us	1	1	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	829.283us	1	1	100.00
	rv_dm_debug_disabled	30.000s	54.503us	1	1	100.00
sec_cm_lc_dft_en_intersig_mubi				2	2	100.00
	rv_dm_sba_debug_disabled	31.000s	829.283us	1	1	100.00
	rv_dm_debug_disabled	30.000s	54.503us	1	1	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				1	1	100.00
	rv_dm_smoke	38.000s	3367.504us	1	1	100.00
sec_cm_dm_en_ctrl_lc_gated				1	1	100.00
	rv_dm_buffered_enable	32.000s	506.399us	1	1	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	211.759us	1	1	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				1	1	100.00
	rv_dm_sparse_lc_gate_fsm	31.000s	211.759us	1	1	100.00
sec_cm_exec_ctrl_mubi				1	1	100.00
	rv_dm_buffered_enable	32.000s	506.399us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	rv_dm_stress_all_with_rand_reset	41.000s	3990.632us	0	1	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	268.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				2 test runs
	rv_dm_sba_tl_access	114833098430133256165184984212487338496159320225178133797647407403470767838039	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_bad_sba_tl_access	56505598789761960044469261392413069727744771659997320270670453087249689231076	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				2 test runs
	rv_dm_hart_unavail	76015343605729040017437992559360641943677792724488988134850629494759844995332	87	UVM_INFO @ 229163899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	84459255733458401314899599673033837232981800313472933733041141505583549747795	89	UVM_INFO @ 826565542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				1 test run
	rv_dm_delayed_resp_sba_tl_access	97772902879380656974611751075563144245125392089107219370233888087833315808207	107	UVM_INFO @ 74509074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				1 test run
	rv_dm_mem_tl_access_resuming	54574558209794356854780220619797248276595568529620819237665740762100873623023	87	UVM_INFO @ 227060663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				1 test run
	rv_dm_jtag_dmi_debug_disabled	19106075715937570210347066378432214647070108705930815189260843956978177093547	87	UVM_INFO @ 124446985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	rv_dm_scanmode	65341467134069779652408065099448244159413864514516061170770828125768952698224	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				1 test run
	rv_dm_stress_all_with_rand_reset	48235041404960799620070638206969976753506672316764120644490309314273236755167	106	UVM_INFO @ 3990632479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---