Simulation Results: spi_device/1r1w

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.67 %
  • code
  • 88.78 %
  • assert
  • 95.40 %
  • func
  • 72.81 %
  • block
  • 98.37 %
  • line
  • 98.78 %
  • branch
  • 97.05 %
  • toggle
  • 69.73 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 315.000s 53818.313us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 169.214us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 73.698us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.000s 9272.842us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 20.000s 1102.714us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 276.601us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 73.698us 1 1 100.00
spi_device_csr_aliasing 20.000s 1102.714us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 11.948us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 195.944us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 26.119us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 1.000s 3.031us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.358us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 144.706us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 144.706us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 11.000s 3415.420us 1 1 100.00
spi_device_tpm_sts_read 2.000s 60.001us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 58.000s 10370.036us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 10.000s 754.681us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 12395.296us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 20.000s 12395.296us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.000s 638.462us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.000s 638.462us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.000s 638.462us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.000s 638.462us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.000s 638.462us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.000s 489.328us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 116.000s 12013.374us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 116.000s 12013.374us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 116.000s 12013.374us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 18.000s 15833.900us 1 1 100.00
spi_device_read_buffer_direct 14.000s 1306.667us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 116.000s 12013.374us 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 73.000s 16558.313us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 7.000s 1737.577us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 7.000s 1737.577us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 47.000s 2315.180us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 315.000s 53818.313us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 182.000s 48770.557us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 2.000s 239.239us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 63.963us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 53.057us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.000s 1246.131us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.000s 1246.131us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 169.214us 1 1 100.00
spi_device_csr_rw 3.000s 73.698us 1 1 100.00
spi_device_csr_aliasing 20.000s 1102.714us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 1915.953us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 169.214us 1 1 100.00
spi_device_csr_rw 3.000s 73.698us 1 1 100.00
spi_device_csr_aliasing 20.000s 1102.714us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 1915.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 354.119us 1 1 100.00
spi_device_tl_intg_err 15.000s 1385.634us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 15.000s 1385.634us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 12217680955171476551025653541663792355989868601503617167917944781901894456114 87
UVM_ERROR @ 2151286 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[898] not found within the scope .
UVM_ERROR @ 2151286 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[898] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 113128743566675837212908300990708596715249108750197950183872476202106205430949 85
UVM_ERROR @ 842356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xd48182 [110101001000000110000010] vs 0x0 [0])
UVM_ERROR @ 937356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x42c15f [10000101100000101011111] vs 0x0 [0])
UVM_ERROR @ 1003356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb89859 [101110001001100001011001] vs 0x0 [0])
UVM_ERROR @ 1070356 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5b1fb4 [10110110001111110110100] vs 0x0 [0])