| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_host_smoke | 8.000s | 2120.827us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 84.972us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 70.359us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_host_csr_bit_bash | 3.000s | 1154.765us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_host_csr_aliasing | 2.000s | 136.547us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_mem_rw_with_rand_reset | 1.000s | 27.631us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_host_csr_rw | 1.000s | 70.359us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 136.547us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_host_mem_walk | 1.000s | 14.572us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_host_mem_partial_access | 1.000s | 21.713us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| performance | 1 | 1 | 100.00 | |||
| spi_host_performance | 2.000s | 38.802us | 1 | 1 | 100.00 | |
| error_event_intr | 3 | 3 | 100.00 | |||
| spi_host_overflow_underflow | 2.000s | 53.916us | 1 | 1 | 100.00 | |
| spi_host_error_cmd | 1.000s | 18.588us | 1 | 1 | 100.00 | |
| spi_host_event | 101.000s | 63393.237us | 1 | 1 | 100.00 | |
| clock_rate | 1 | 1 | 100.00 | |||
| spi_host_speed | 7.000s | 1211.875us | 1 | 1 | 100.00 | |
| speed | 1 | 1 | 100.00 | |||
| spi_host_speed | 7.000s | 1211.875us | 1 | 1 | 100.00 | |
| chip_select_timing | 1 | 1 | 100.00 | |||
| spi_host_speed | 7.000s | 1211.875us | 1 | 1 | 100.00 | |
| upper_range_clkdiv | 1 | 1 | 100.00 | |||
| spi_host_upper_range_clkdiv | 47.000s | 1863.655us | 1 | 1 | 100.00 | |
| sw_reset | 1 | 1 | 100.00 | |||
| spi_host_sw_reset | 2.000s | 56.974us | 1 | 1 | 100.00 | |
| passthrough_mode | 1 | 1 | 100.00 | |||
| spi_host_passthrough_mode | 1.000s | 69.132us | 1 | 1 | 100.00 | |
| cpol_cpha | 1 | 1 | 100.00 | |||
| spi_host_speed | 7.000s | 1211.875us | 1 | 1 | 100.00 | |
| full_cycle | 1 | 1 | 100.00 | |||
| spi_host_speed | 7.000s | 1211.875us | 1 | 1 | 100.00 | |
| duplex | 1 | 1 | 100.00 | |||
| spi_host_smoke | 8.000s | 2120.827us | 1 | 1 | 100.00 | |
| tx_rx_only | 1 | 1 | 100.00 | |||
| spi_host_smoke | 8.000s | 2120.827us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_host_stress_all | 20.000s | 1024.480us | 1 | 1 | 100.00 | |
| spien | 1 | 1 | 100.00 | |||
| spi_host_spien | 15.000s | 6939.556us | 1 | 1 | 100.00 | |
| stall | 1 | 1 | 100.00 | |||
| spi_host_status_stall | 259.000s | 24405.126us | 1 | 1 | 100.00 | |
| Idlecsbactive | 1 | 1 | 100.00 | |||
| spi_host_idlecsbactive | 2.000s | 97.481us | 1 | 1 | 100.00 | |
| data_fifo_status | 1 | 1 | 100.00 | |||
| spi_host_overflow_underflow | 2.000s | 53.916us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_host_alert_test | 1.000s | 15.588us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_host_intr_test | 1.000s | 27.611us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 1.000s | 241.540us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 1.000s | 241.540us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 84.972us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 70.359us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 136.547us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 1.000s | 75.011us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 84.972us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 1.000s | 70.359us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 136.547us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 1.000s | 75.011us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_host_tl_intg_err | 2.000s | 169.106us | 1 | 1 | 100.00 | |
| spi_host_sec_cm | 2.000s | 70.549us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_host_tl_intg_err | 2.000s | 169.106us | 1 | 1 | 100.00 | |