Simulation Results: sram_ctrl/ret

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.02 %
  • code
  • 81.80 %
  • assert
  • 97.26 %
  • func
  • 94.00 %
  • block
  • 93.08 %
  • line
  • 94.09 %
  • branch
  • 88.11 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
87.50%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 182.066us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 15.678us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.565us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 680.517us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.954us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 97.925us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.565us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.954us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 394.894us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 95.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 10.000s 903.331us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 189.000s 8417.379us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 536.663us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 6.000s 627.612us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 6490.580us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 3224.907us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 119.055us 1 1 100.00
sram_ctrl_partial_access_b2b 196.000s 15867.981us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 2.000s 49.593us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 113.278us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 63.466us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 10.000s 750.100us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 112.653us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 27.000s 18299.157us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 39.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 32.251us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 32.251us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.678us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.565us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.954us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 15.678us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.565us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.954us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 13.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 256.226us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 159.249us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 159.249us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 750.100us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 10.000s 750.100us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.565us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 3224.907us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 3224.907us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 3224.907us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 6490.580us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 382.497us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 256.226us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 63.197us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 182.066us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 182.066us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 3224.907us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 6490.580us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 182.066us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 548.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 23.000s 1643.132us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 50847252074528957288725426016357723122822863245014931397033872557120705107961 86
UVM_INFO @ 49593346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 89404851243058950012994841414895481910708114807723150767593355803844131086893 86
UVM_INFO @ 113278124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 19057328302929900042962284572249477837553419326421858968727811498896986178484 86
UVM_INFO @ 63466386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 90403471843107354653810413981916637197998235769147493575374685151480385280616 88
UVM_INFO @ 97924963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---