Simulation Results: uart

 
06/07/2026 19:39:26 DVSim: v1.49.12 sha: 0e745b4 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.98 %
  • code
  • 92.69 %
  • assert
  • 98.56 %
  • func
  • 90.69 %
  • block
  • 99.00 %
  • line
  • 99.52 %
  • branch
  • 98.16 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 3.000s 508.450us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 11.401us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 16.952us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.000s 80.382us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 24.562us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.000s 26.017us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 16.952us 1 1 100.00
uart_csr_aliasing 1.000s 24.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 4.000s 7599.744us 1 1 100.00
parity 2 2 100.00
uart_smoke 3.000s 508.450us 1 1 100.00
uart_tx_rx 4.000s 7599.744us 1 1 100.00
parity_error 2 2 100.00
uart_intr 542.000s 535727.531us 1 1 100.00
uart_rx_parity_err 13.000s 48051.304us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 4.000s 7599.744us 1 1 100.00
uart_intr 542.000s 535727.531us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 15.000s 9438.053us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 174.000s 198879.812us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 9.000s 36768.931us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 542.000s 535727.531us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 542.000s 535727.531us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 542.000s 535727.531us 1 1 100.00
perf 1 1 100.00
uart_perf 128.000s 10412.573us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.000s 1962.594us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.000s 1962.594us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 10.000s 6680.330us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 11.000s 35984.651us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 11.000s 6460.689us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 6.000s 4412.438us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 546.000s 83908.402us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 2.000s 2350.619us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 2.000s 25.621us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 1.000s 37.170us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 89.937us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 89.937us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 11.401us 1 1 100.00
uart_csr_rw 1.000s 16.952us 1 1 100.00
uart_csr_aliasing 1.000s 24.562us 1 1 100.00
uart_same_csr_outstanding 1.000s 285.091us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 11.401us 1 1 100.00
uart_csr_rw 1.000s 16.952us 1 1 100.00
uart_csr_aliasing 1.000s 24.562us 1 1 100.00
uart_same_csr_outstanding 1.000s 285.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 2.000s 249.759us 1 1 100.00
uart_tl_intg_err 1.000s 111.563us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.000s 111.563us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 17.000s 6892.953us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:446) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr 1 test run
uart_stress_all 68932955894189533640931214332943687841256590655519311269969833785015629555514 91
UVM_ERROR @ 196018864 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_ERROR @ 196018864 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 196018864 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark
UVM_ERROR @ 577258864 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0