Simulation Results: ac_range_check

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.82 %
  • code
  • 92.97 %
  • assert
  • 97.75 %
  • func
  • 57.75 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.73 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 2028.663us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 41.000s 2376.309us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 74.926us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 51.747us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 20.000s 724.552us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2936.265us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 1.000s 15.261us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 51.747us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2936.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 65.323us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 21.000s 2026.761us 1 1 100.00
stress_all 0 1 0.00
ac_range_check_stress_all 85.000s 10005.308us 0 1 0.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 29.727us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 16.780us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 102.665us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 102.665us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 74.926us 1 1 100.00
ac_range_check_csr_rw 3.000s 51.747us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2936.265us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 100.192us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 74.926us 1 1 100.00
ac_range_check_csr_rw 3.000s 51.747us 1 1 100.00
ac_range_check_csr_aliasing 18.000s 2936.265us 1 1 100.00
ac_range_check_same_csr_outstanding 3.000s 100.192us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 458.216us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 458.216us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 458.216us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 10.000s 458.216us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 89.000s 5422.605us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 1.000s 21.443us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 1749.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 270.000s 33246.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 19.000s 418.439us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_stress_all 23011743366105016491438540161208745430508238633230384353367964597056436054571 8402
UVM_INFO @ 10005307986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---