Simulation Results: aes/gcm_masked

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.95 %
  • code
  • 95.52 %
  • assert
  • 98.29 %
  • func
  • 70.03 %
  • block
  • 96.32 %
  • line
  • 97.40 %
  • branch
  • 91.13 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 4.000s 318.823us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 65.001us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 66.718us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 73.514us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 1272.758us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 130.339us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 53.121us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 73.514us 1 1 100.00
aes_csr_aliasing 2.000s 130.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 65.001us 1 1 100.00
aes_config_error 4.000s 279.642us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 65.001us 1 1 100.00
aes_config_error 4.000s 279.642us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_b2b 8.000s 203.733us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 65.001us 1 1 100.00
aes_config_error 4.000s 279.642us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 89.977us 1 1 100.00
aes_config_error 4.000s 279.642us 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 248.747us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 321.634us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 7.000s 570.693us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_sideload 4.000s 502.384us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 228.785us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 227.000s 13708.625us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 209.013us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 59.905us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 176.389us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 176.389us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 66.718us 1 1 100.00
aes_csr_rw 2.000s 73.514us 1 1 100.00
aes_csr_aliasing 2.000s 130.339us 1 1 100.00
aes_same_csr_outstanding 2.000s 60.696us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 66.718us 1 1 100.00
aes_csr_rw 2.000s 73.514us 1 1 100.00
aes_csr_aliasing 2.000s 130.339us 1 1 100.00
aes_same_csr_outstanding 2.000s 60.696us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 3.000s 83.661us 0 1 0.00
fault_inject 1 3 33.33
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 669.840us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 2585.420us 1 1 100.00
aes_tl_intg_err 2.000s 132.851us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 132.851us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 65.001us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
aes_core_fi 4.000s 525.107us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 209.013us 1 1 100.00
aes_config_error 4.000s 279.642us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_core_fi 4.000s 525.107us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 439.379us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 103.107us 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 313.444us 1 1 100.00
aes_sideload 4.000s 502.384us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 103.107us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 103.107us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 103.107us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 103.107us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 103.107us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 313.444us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 5.000s 131.115us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 5.000s 131.115us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 5.000s 131.115us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 5.000s 131.115us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 457.327us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 54.486us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 105.416us 1 1 100.00
aes_fi 5.000s 131.115us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 5.000s 131.115us 0 1 0.00
aes_control_fi 61.000s 0.000us 0 1 0.00
aes_cipher_fi 2.000s 66.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 6.000s 350.803us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 3591097327720485853446696887165125183037634781352482801118315318867188299458 2998
UVM_INFO @ 83661396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 4337711676183062168907232481092731597252113791000901022386476348153314029111 23718
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_control_fi 42819095418588734879326732106817130778728452678672764862751939999224695487096 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 80223508984540163664865146604691005802075754862726194478172835490473100194955 259
UVM_INFO @ 350802819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---