Simulation Results: aes/gcm_unmasked

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.25 %
  • code
  • 90.80 %
  • assert
  • 97.75 %
  • func
  • 64.20 %
  • block
  • 90.23 %
  • line
  • 92.10 %
  • branch
  • 82.31 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 66.270us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 66.096us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 80.721us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 67.166us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 453.876us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 140.311us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 265.707us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 67.166us 1 1 100.00
aes_csr_aliasing 3.000s 140.311us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 66.096us 1 1 100.00
aes_config_error 3.000s 106.293us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 66.096us 1 1 100.00
aes_config_error 3.000s 106.293us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_b2b 4.000s 146.277us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 66.096us 1 1 100.00
aes_config_error 3.000s 106.293us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 71.640us 1 1 100.00
aes_config_error 3.000s 106.293us 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 340.655us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 127.465us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_sideload 2.000s 127.099us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 698.987us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.072s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 66.473us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 89.616us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 89.616us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.721us 1 1 100.00
aes_csr_rw 1.000s 67.166us 1 1 100.00
aes_csr_aliasing 3.000s 140.311us 1 1 100.00
aes_same_csr_outstanding 2.000s 178.161us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.721us 1 1 100.00
aes_csr_rw 1.000s 67.166us 1 1 100.00
aes_csr_aliasing 3.000s 140.311us 1 1 100.00
aes_same_csr_outstanding 2.000s 178.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 61.363us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 136.409us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 367.043us 1 1 100.00
aes_tl_intg_err 2.000s 119.607us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 119.607us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 66.096us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
aes_core_fi 2.000s 111.429us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 106.293us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_core_fi 2.000s 111.429us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 174.489us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 54.323us 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 314.534us 1 1 100.00
aes_sideload 2.000s 127.099us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 54.323us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 54.323us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 54.323us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 54.323us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 54.323us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 314.534us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2326.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2326.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2326.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2326.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 3.000s 124.157us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_ctr_fi 2.000s 62.433us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2326.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 2326.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 52.113us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 1.000s 24.081us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
aes_cipher_fi 4139659197707531897123479251623337636082793064315156184576253671963843028501 None
aes_stress_all 57744959699531040798010846381300718217868885976036318785244785231087653037210 None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 74278618863211385512917824999484135405116885303963102454465398602783591403095 10306333
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:104) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 77248813812588677490634543310428879220214142789876282591090711525338221638252 112
UVM_INFO @ 24080538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---