Simulation Results: clkmgr

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.86 %
  • code
  • 67.39 %
  • assert
  • 88.02 %
  • func
  • 57.18 %
  • line
  • 81.20 %
  • branch
  • 85.86 %
  • cond
  • 74.72 %
  • toggle
  • 95.19 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
12.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.550s 112.059us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 17.998us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 1.540s 68.492us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.690s 2.524us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.840s 13.559us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
clkmgr_csr_aliasing 0.690s 2.524us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.840s 13.085us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.630s 121.286us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.790s 23.328us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.550s 112.059us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.670s 10.623us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.730s 2.430us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.670s 10.623us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 2.400s 157.943us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.010s 14.890us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.570s 104.896us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.570s 104.896us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 0.750s 17.998us 1 1 100.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
clkmgr_csr_aliasing 0.690s 2.524us 0 1 0.00
clkmgr_same_csr_outstanding 0.900s 15.277us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 0.750s 17.998us 1 1 100.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
clkmgr_csr_aliasing 0.690s 2.524us 0 1 0.00
clkmgr_same_csr_outstanding 0.900s 15.277us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 90.980s 10014.069us 0 1 0.00
clkmgr_tl_intg_err 0.810s 9.373us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 1600.900s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 1600.900s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 1600.900s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 1600.900s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.740s 11.116us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.810s 9.373us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.670s 10.623us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.730s 2.430us 0 1 0.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 1600.900s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.180s 64.607us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 90.980s 10014.069us 0 1 0.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.630s 4.465us 0 1 0.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 90.980s 10014.069us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.940s 21.509us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.680s 24.635us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency_timeout 30859215545521181899235871281697388163858392967560023055644695147952861577524 77
UVM_INFO @ 2430223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 57800304431716600111605714938950553068016890185238523163168347537922370557385 91
UVM_INFO @ 24635057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 4572232269930148110604084388316021875746214589501786574536586282814166050897 145
UVM_INFO @ 157942843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 3 test runs
clkmgr_tl_intg_err 72665073476966586149256013388789069878954371973650774280625761820309548168942 85
UVM_INFO @ 9372950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 48134701132664508394070449363149799022289957521001947072809308959732572402511 76
UVM_INFO @ 4465491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 20161345078964037379359194640145231935321762428795309612490196331434465934457 75
UVM_INFO @ 2524125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 35798973682528444023813004529161920331169330758836207524091516128245271147362 75
UVM_INFO @ 11115890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 96683593731001308625569183725309001112504569541067571894561408010413862452302 76
UVM_INFO @ 13559277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency 51308362079514633362512244191263306304395022428018895377917445527636981447440 76
UVM_INFO @ 10622609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 113749556560893989892089060863678927031444735370420709472302005313332157391545 74
UVM_INFO @ 21508789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 109546851246885116411268762272625284506983561409812595942166006810935460196463 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 99017042740397100628882556904091771902516583846692944866951606190963609316521 85
UVM_INFO @ 10014069452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 16911145783501049896296119854750869404580897996345026338485887435888357046792 75
UVM_INFO @ 68491759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 69460850215356664571149202025988624538641326987749310827216986416885602695992 75
UVM_INFO @ 15276777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---