Simulation Results: dma

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.06 %
  • code
  • 90.76 %
  • assert
  • 96.50 %
  • func
  • 61.93 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 302.097us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 3.000s 1053.014us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 5.000s 593.424us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 43.971us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 61.959us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 7971.333us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 229.494us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 41.794us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 61.959us 1 1 100.00
dma_csr_aliasing 4.000s 229.494us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 45.000s 3280.858us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 577.000s 250306.171us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 152.000s 114719.147us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 152.000s 114719.147us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 577.000s 250306.171us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 74.000s 7314.810us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 152.000s 114719.147us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 11.000s 1164.904us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 65.000s 6466.007us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 60.004us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 13.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 113.065us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 113.065us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 43.971us 1 1 100.00
dma_csr_rw 1.000s 61.959us 1 1 100.00
dma_csr_aliasing 4.000s 229.494us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.009us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 43.971us 1 1 100.00
dma_csr_rw 1.000s 61.959us 1 1 100.00
dma_csr_aliasing 4.000s 229.494us 1 1 100.00
dma_same_csr_outstanding 2.000s 73.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 19.000s 240.678us 1 1 100.00
dma_generic_stress 74.000s 7314.810us 1 1 100.00
dma_handshake_stress 152.000s 114719.147us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 5060.021us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 107.986us 1 1 100.00
dma_sec_cm 1.000s 38.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 136.000s 34911.897us 1 1 100.00
dma_longer_transfer 12.000s 616.132us 1 1 100.00
dma_stress_all_with_rand_reset 9.000s 398.315us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 9737820443901242252490155098220908769094698880540984932398250649677810117090 109
UVM_INFO @ 398315295ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---