Simulation Results: edn/edn0

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 75.70 %
  • code
  • 84.17 %
  • assert
  • 94.25 %
  • func
  • 48.67 %
  • block
  • 93.77 %
  • line
  • 96.78 %
  • branch
  • 86.65 %
  • toggle
  • 73.41 %
  • FSM
  • 79.84 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.000s 54.655us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 110.534us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 11.318us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.000s 50.975us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 235.384us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 38.470us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 11.318us 1 1 100.00
edn_csr_aliasing 2.000s 235.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 3.000s 264.397us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 3.000s 264.397us 1 1 100.00
genbits 1 1 100.00
edn_genbits 3.000s 264.397us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 46.707us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 26.181us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 19.912us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 75.735us 1 1 100.00
edn_disable_auto_req_mode 2.000s 36.517us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 5.000s 375.383us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.000s 97.968us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 2.000s 75.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.000s 127.554us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.000s 127.554us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 110.534us 1 1 100.00
edn_csr_rw 1.000s 11.318us 1 1 100.00
edn_csr_aliasing 2.000s 235.384us 1 1 100.00
edn_same_csr_outstanding 1.000s 32.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 110.534us 1 1 100.00
edn_csr_rw 1.000s 11.318us 1 1 100.00
edn_csr_aliasing 2.000s 235.384us 1 1 100.00
edn_same_csr_outstanding 1.000s 32.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
edn_tl_intg_err 1.000s 55.258us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 18.196us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 26.181us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 26.181us 1 1 100.00
edn_sec_cm 4.000s 491.780us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 26.181us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.000s 55.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 17.000s 1037.336us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 18943908069469353721789794635831732753271969380855488557195291420789257726508 193
UVM_INFO @ 1037335997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---