Simulation Results: edn/edn1

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 82.84 %
  • assert
  • 98.70 %
  • func
  • 79.62 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 89.54 %
  • toggle
  • 87.23 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 126.281us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 27.611us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.970s 18.522us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.720s 1542.610us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 44.373us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.710s 218.626us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.970s 18.522us 1 1 100.00
edn_csr_aliasing 1.030s 44.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.500s 55.595us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.500s 55.595us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.500s 55.595us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 28.860us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.900s 42.137us 1 1 100.00
errs 1 1 100.00
edn_err 0.920s 20.376us 1 1 100.00
disable 2 2 100.00
edn_disable 0.760s 47.728us 1 1 100.00
edn_disable_auto_req_mode 0.870s 163.915us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.550s 339.370us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 109.379us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 14.244us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.810s 120.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.810s 120.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 27.611us 1 1 100.00
edn_csr_rw 0.970s 18.522us 1 1 100.00
edn_csr_aliasing 1.030s 44.373us 1 1 100.00
edn_same_csr_outstanding 1.160s 37.514us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 27.611us 1 1 100.00
edn_csr_rw 0.970s 18.522us 1 1 100.00
edn_csr_aliasing 1.030s 44.373us 1 1 100.00
edn_same_csr_outstanding 1.160s 37.514us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
edn_tl_intg_err 1.440s 109.932us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.020s 29.120us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.900s 42.137us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.900s 42.137us 1 1 100.00
edn_sec_cm 3.970s 356.048us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.900s 42.137us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.440s 109.932us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 21.660s 1538.027us 1 1 100.00