Simulation Results: hmac

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.91 %
  • code
  • 95.86 %
  • assert
  • 96.30 %
  • func
  • 29.56 %
  • block
  • 97.32 %
  • line
  • 98.35 %
  • branch
  • 93.29 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.000s 222.945us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 310.901us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 1.000s 42.204us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.000s 1386.773us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 438.344us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 48.041us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 1.000s 42.204us 1 1 100.00
hmac_csr_aliasing 3.000s 438.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 50.000s 5065.638us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 35.000s 1074.812us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.000s 928.934us 1 1 100.00
hmac_test_sha384_vectors 444.000s 71191.891us 1 1 100.00
hmac_test_sha512_vectors 438.000s 75044.797us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 473.234us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1750.453us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1438.997us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 7.000s 1027.148us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 92.000s 2810.503us 1 1 100.00
error 1 1 100.00
hmac_error 5.000s 4959.966us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 42.000s 4719.343us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.000s 222.945us 1 1 100.00
hmac_long_msg 50.000s 5065.638us 1 1 100.00
hmac_back_pressure 35.000s 1074.812us 1 1 100.00
hmac_datapath_stress 92.000s 2810.503us 1 1 100.00
hmac_burst_wr 7.000s 1027.148us 1 1 100.00
hmac_stress_all 237.000s 72795.992us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.000s 222.945us 1 1 100.00
hmac_long_msg 50.000s 5065.638us 1 1 100.00
hmac_back_pressure 35.000s 1074.812us 1 1 100.00
hmac_datapath_stress 92.000s 2810.503us 1 1 100.00
hmac_wipe_secret 42.000s 4719.343us 1 1 100.00
hmac_test_sha256_vectors 9.000s 928.934us 1 1 100.00
hmac_test_sha384_vectors 444.000s 71191.891us 1 1 100.00
hmac_test_sha512_vectors 438.000s 75044.797us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 473.234us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1750.453us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1438.997us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.000s 222.945us 1 1 100.00
hmac_long_msg 50.000s 5065.638us 1 1 100.00
hmac_back_pressure 35.000s 1074.812us 1 1 100.00
hmac_datapath_stress 92.000s 2810.503us 1 1 100.00
hmac_burst_wr 7.000s 1027.148us 1 1 100.00
hmac_error 5.000s 4959.966us 1 1 100.00
hmac_wipe_secret 42.000s 4719.343us 1 1 100.00
hmac_test_sha256_vectors 9.000s 928.934us 1 1 100.00
hmac_test_sha384_vectors 444.000s 71191.891us 1 1 100.00
hmac_test_sha512_vectors 438.000s 75044.797us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 473.234us 1 1 100.00
hmac_test_hmac384_vectors 9.000s 1750.453us 1 1 100.00
hmac_test_hmac512_vectors 14.000s 1438.997us 1 1 100.00
hmac_stress_all 237.000s 72795.992us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 237.000s 72795.992us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 33.631us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 41.305us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 756.325us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 756.325us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 310.901us 1 1 100.00
hmac_csr_rw 1.000s 42.204us 1 1 100.00
hmac_csr_aliasing 3.000s 438.344us 1 1 100.00
hmac_same_csr_outstanding 1.000s 223.562us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 310.901us 1 1 100.00
hmac_csr_rw 1.000s 42.204us 1 1 100.00
hmac_csr_aliasing 3.000s 438.344us 1 1 100.00
hmac_same_csr_outstanding 1.000s 223.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 139.017us 1 1 100.00
hmac_tl_intg_err 5.000s 1085.487us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 5.000s 1085.487us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.000s 222.945us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.000s 137.828us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 38.000s 3918.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 113.069us 1 1 100.00