Simulation Results

Simulation Results: i2c

07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
87.55 %

code
85.62 %

assert
97.46 %

func
79.57 %

block
95.87 %

line
95.26 %

branch
92.58 %

toggle
72.64 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	101.000s	1870.085us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	14.000s	805.078us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	22.510us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	1.000s	85.373us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.000s	356.806us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	29.039us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.000s	55.660us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	1.000s	85.373us	1	1	100.00
	i2c_csr_aliasing	2.000s	29.039us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	54.616us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	110.000s	18368.494us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	144.000s	3133.575us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	2.000s	29.793us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1873.000s	4749.003us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	2.000s	214.956us	1	1	100.00
	i2c_host_fifo_fmt_empty	13.000s	2080.774us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	229.060us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	787.000s	16138.019us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	28.000s	3389.904us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	14.133us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	4.000s	1008.163us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.000s	420.552us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	14.000s	1024.310us	1	1	100.00
	i2c_target_intr_smoke	7.000s	651.757us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	3.000s	615.814us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	229.863us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	14.000s	1024.310us	1	1	100.00
	i2c_target_intr_stress_wr	174.000s	5551.951us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	13.000s	22258.983us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	4.000s	1337.696us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.000s	378.792us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	9.000s	10401.227us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	4348.755us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	300.258us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	144.000s	3133.575us	1	1	100.00
	i2c_host_perf_precise	7.000s	232.971us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	28.000s	3389.904us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	342.372us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	1919.431us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	539.963us	1	1	100.00
	i2c_target_nack_txstretch	2.000s	565.199us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.000s	875.677us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	4.000s	531.482us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	2.000s	56.451us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	25.543us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.000s	49.186us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.000s	49.186us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.510us	1	1	100.00
	i2c_csr_rw	1.000s	85.373us	1	1	100.00
	i2c_csr_aliasing	2.000s	29.039us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	28.244us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	22.510us	1	1	100.00
	i2c_csr_rw	1.000s	85.373us	1	1	100.00
	i2c_csr_aliasing	2.000s	29.039us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	28.244us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.000s	530.271us	1	1	100.00
	i2c_sec_cm	2.000s	116.408us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.000s	530.271us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	9.000s	2876.866us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	1294.244us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.000s	995.652us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	85526556028604180983880800665629850576348423939127614589311448549961590625192	None
	i2c_target_stress_wr	96879535464976584925272786597943523190693526710685050346492970821953460425180	None
	i2c_target_stress_all	88089508132855302073703676714099664235524052980913279765423330960803888947390	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	29924965570847526196142491764999212607682661029577339972280861044008354713543	89	UVM_INFO @ 54615596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	36266464931957520014260414811020039304994469838505732758052381608247270827938	112	UVM_INFO @ 995651928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	98132731476919875555983547927575330672229737980185708133127174426401311341925	90	UVM_INFO @ 14132714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.fmtfull (addr=, Comparison=CompareOpEq, exp_data=, call_count=1950)				1 test run
	i2c_host_stress_all	17221823133990088010071541357925574829078314696285200229603099650992687742417	183	UVM_INFO @ 18368493872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	97256025889814001932612750034895839398398195449066088874487811803134789724297	93	UVM_INFO @ 1008162993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	13156657274833629566894995532251663910396622063366048003749109287776941227324	87	UVM_INFO @ 1294243602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	65738312892410224145976855124643392600170101586814694543204557298739674816341	88	UVM_INFO @ 10401226831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	42890238546341026510322724657907204162426127195041461364535986788173054406987	136	UVM_INFO @ 2876865562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---