Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.97 %
  • code
  • 92.91 %
  • assert
  • 96.69 %
  • func
  • 86.31 %
  • block
  • 96.61 %
  • line
  • 97.29 %
  • branch
  • 91.38 %
  • toggle
  • 87.71 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 38.572us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 16.324us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.999us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 106.346us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 85.368us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 41.406us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 54.999us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 85.368us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.000s 92.045us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 175.028us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.473us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 59.456us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.000s 3446.028us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_prog_failure 2.000s 59.456us 1 1 100.00
lc_ctrl_errors 8.000s 3446.028us 1 1 100.00
lc_ctrl_security_escalation 5.000s 1926.964us 1 1 100.00
lc_ctrl_jtag_state_failure 2.000s 378.279us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 578.435us 1 1 100.00
lc_ctrl_jtag_errors 29.000s 2325.486us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 3366.666us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1897.134us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.000s 578.435us 1 1 100.00
lc_ctrl_jtag_errors 29.000s 2325.486us 1 1 100.00
lc_ctrl_jtag_access 6.000s 2880.577us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.000s 2832.018us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 167.812us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 201.834us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 29.000s 2673.044us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.000s 2206.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 58.893us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 2829.504us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 26.615us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.000s 653.812us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 22.381us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 83.000s 4985.383us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 16.965us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 48.901us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 48.901us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 16.324us 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.999us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 85.368us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 106.094us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 16.324us 1 1 100.00
lc_ctrl_csr_rw 1.000s 54.999us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 85.368us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.000s 106.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 695.796us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 4.000s 695.796us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.000s 175.028us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.000s 575.887us 1 1 100.00
lc_ctrl_sec_cm 2.000s 498.165us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1926.964us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.000s 92.045us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.000s 1897.134us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 901.024us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.000s 901.024us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 1086.482us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 343.436us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 343.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 19.000s 7169.980us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 92174166730912326524295375485478597687602994528896801542716891222648861183332 177
UVM_INFO @ 378279010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all_with_rand_reset 75522386029215407214965150953703790605662055414273341608590473986072958664119 1033
UVM_INFO @ 7169980198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---