Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.84 %
  • code
  • 93.25 %
  • assert
  • 95.97 %
  • func
  • 86.31 %
  • block
  • 97.02 %
  • line
  • 97.60 %
  • branch
  • 92.45 %
  • toggle
  • 87.73 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.000s 19.283us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 33.079us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.141us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 981.696us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 26.331us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 16.141us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.000s 604.989us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 3842.555us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 14.572us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.000s 183.125us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.000s 680.104us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_prog_failure 3.000s 183.125us 1 1 100.00
lc_ctrl_errors 4.000s 680.104us 1 1 100.00
lc_ctrl_security_escalation 5.000s 1226.773us 1 1 100.00
lc_ctrl_jtag_state_failure 34.000s 1984.091us 1 1 100.00
lc_ctrl_jtag_prog_failure 14.000s 1708.219us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 4942.432us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.000s 63.318us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 2549.653us 1 1 100.00
lc_ctrl_jtag_prog_failure 14.000s 1708.219us 1 1 100.00
lc_ctrl_jtag_errors 18.000s 4942.432us 1 1 100.00
lc_ctrl_jtag_access 4.000s 852.328us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.000s 852.606us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 401.280us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.000s 294.151us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.000s 764.533us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.000s 437.003us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 22.706us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 576.592us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 174.352us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.000s 1822.719us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 18.331us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 54.000s 3771.225us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 29.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 365.700us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 365.700us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 33.079us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.141us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 16.853us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.000s 33.079us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.141us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 37.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 16.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 470.156us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 470.156us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 3842.555us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 4.000s 1120.972us 1 1 100.00
lc_ctrl_sec_cm 4.000s 967.411us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1226.773us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.000s 604.989us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.000s 2549.653us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 266.762us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.000s 266.762us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 2768.865us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 592.020us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.000s 592.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 21.000s 5858.266us 1 1 100.00