Simulation Results: mbx

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.08 %
  • code
  • 88.90 %
  • assert
  • 97.05 %
  • func
  • 75.29 %
  • block
  • 96.50 %
  • line
  • 96.36 %
  • branch
  • 90.81 %
  • toggle
  • 79.52 %
Validation stages
V1
83.33%
V2
63.64%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 45.000s 7881.736us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 47.436us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 23.187us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 3.000s 176.668us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 1.000s 15.737us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 18.599us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 23.187us 1 1 100.00
mbx_csr_aliasing 1.000s 15.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 1.000s 46.601us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 1.000s 9.587us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 59.000s 20471.860us 1 1 100.00
mbx_doe_intr_msg 0 1 0.00
mbx_doe_intr_msg 7.000s 1486.033us 0 1 0.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 20.206us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 42.795us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 4.512us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 4.512us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 47.436us 1 1 100.00
mbx_csr_rw 1.000s 23.187us 1 1 100.00
mbx_csr_aliasing 1.000s 15.737us 1 1 100.00
mbx_same_csr_outstanding 2.000s 181.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 47.436us 1 1 100.00
mbx_csr_rw 1.000s 23.187us 1 1 100.00
mbx_csr_aliasing 1.000s 15.737us 1 1 100.00
mbx_same_csr_outstanding 2.000s 181.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 203.208us 1 1 100.00
mbx_sec_cm 2.000s 33.064us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 29538518537563249036027713405487140990732474380930838831606693634798267788349 92
UVM_INFO @ 46600806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 50924028054477563852047885670976878702308589089133268016260927127206029519063 127
UVM_INFO @ 9586808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:582) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 91208599392828267638081043235652758828785667529912186190756647093701839896746 85
TL item was: req: (cip_tl_seq_item@18682) { a_addr: 'hb3cd5d10 a_data: 'ha38351a5 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'hce a_opcode: 'h0 a_user: 'h27196 d_param: 'h0 d_source: 'hce d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 4511550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 114735260719632624102025830759832538813339074570388919595543134970533601842987 86
TL item was: req: (cip_tl_seq_item@19315) { a_addr: 'h6a949494 a_data: 'hcf6cbfc7 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'h9d a_opcode: 'h1 a_user: 'h24ef9 d_param: 'h0 d_source: 'h9d d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 18599346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (mbx_doe_intr_msg_vseq.sv:56) [_item] Check failed act_data == data[i] (* [*] vs * [*]) DOE_INTR_MSG_DATA does not have the expected value 1 test run
mbx_doe_intr_msg 32750826695379320643729777657543505461910499032014086773505639731092040360256 83
UVM_INFO @ 1486033119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---