Simulation Results: otbn

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.91 %
  • code
  • 81.12 %
  • assert
  • 87.68 %
  • func
  • 94.92 %
  • block
  • 97.73 %
  • line
  • 97.91 %
  • branch
  • 81.93 %
  • toggle
  • 81.27 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 279.837us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 147.717us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 21.611us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 6.000s 80.999us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 30.017us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 8.000s 37.543us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 21.611us 1 1 100.00
otbn_csr_aliasing 4.000s 30.017us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 34.000s 3107.628us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 29.000s 1211.099us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 39.000s 126.567us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 61.000s 162.852us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 25.000s 259.287us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 72.000s 329.080us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 9.000s 30.794us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 5.000s 20.392us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 9.000s 26.281us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 5.000s 21.650us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 29.423us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 51.267us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 51.267us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 147.717us 1 1 100.00
otbn_csr_rw 3.000s 21.611us 1 1 100.00
otbn_csr_aliasing 4.000s 30.017us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 147.717us 1 1 100.00
otbn_csr_rw 3.000s 21.611us 1 1 100.00
otbn_csr_aliasing 4.000s 30.017us 1 1 100.00
otbn_same_csr_outstanding 3.000s 17.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 9.000s 68.376us 1 1 100.00
otbn_dmem_err 7.000s 44.375us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 8.000s 48.238us 0 1 0.00
otbn_controller_ispr_rdata_err 5.000s 28.610us 1 1 100.00
otbn_mac_bignum_acc_err 12.000s 67.592us 1 1 100.00
otbn_urnd_err 5.000s 10.496us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 35.516us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 13.606us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 192.470us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
otbn_tl_intg_err 13.000s 320.376us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 75.000s 344.715us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 279.837us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 44.375us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 9.000s 68.376us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 13.000s 320.376us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 30.794us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 68.376us 1 1 100.00
otbn_dmem_err 7.000s 44.375us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 20.392us 1 1 100.00
otbn_illegal_mem_acc 9.000s 35.516us 1 1 100.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 68.376us 1 1 100.00
otbn_dmem_err 7.000s 44.375us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 20.392us 1 1 100.00
otbn_illegal_mem_acc 9.000s 35.516us 1 1 100.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 9.000s 30.794us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 9.000s 68.376us 1 1 100.00
otbn_dmem_err 7.000s 44.375us 1 1 100.00
otbn_zero_state_err_urnd 5.000s 20.392us 1 1 100.00
otbn_illegal_mem_acc 9.000s 35.516us 1 1 100.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 9.000s 24.895us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 46.704us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 23.000s 80.932us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 23.000s 80.932us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 30.138us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 58.480us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 19.000s 175.782us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 19.000s 175.782us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 26.022us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 25.000s 259.287us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 55.885us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 26.219us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 342.360us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 164.000s 1420.030us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 70.325us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 82466683028142611386870027154889539925189560998177225314057681449711611943951 122
UVM_INFO @ 48238058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 13986857614043968473762482254968913099722509142528833208901995957199591543644 145
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 342360303 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 342360303 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 342360303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---