Simulation Results: otp_ctrl

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.51 %
  • code
  • 71.94 %
  • assert
  • 91.52 %
  • func
  • 54.06 %
  • line
  • 87.20 %
  • branch
  • 82.82 %
  • cond
  • 85.71 %
  • toggle
  • 67.13 %
  • FSM
  • 36.84 %
Validation stages
V1
100.00%
V2
60.00%
V2S
44.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.160s 838.341us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.200s 1707.583us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.610s 106.962us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.950s 1243.640us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 2182.564us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.890s 75.511us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.610s 106.962us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 2182.564us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.680s 90.360us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.430s 59.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 118.150s 7831.442us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.670s 118.583us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 5.330s 1229.822us 0 1 0.00
otp_ctrl_check_fail 25.390s 1628.539us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.160s 2933.189us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 15.600s 1703.259us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 19.390s 786.672us 1 1 100.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 36.960s 2171.948us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 3.220s 112.475us 0 1 0.00
test_access 0 1 0.00
otp_ctrl_test_access 5.800s 206.858us 0 1 0.00
stress_all 0 1 0.00
otp_ctrl_stress_all 13.020s 10352.012us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.260s 50.592us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.890s 75.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 6.910s 3229.493us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 6.910s 3229.493us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.200s 1707.583us 1 1 100.00
otp_ctrl_csr_rw 1.610s 106.962us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 2182.564us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.290s 108.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.200s 1707.583us 1 1 100.00
otp_ctrl_csr_rw 1.610s 106.962us 1 1 100.00
otp_ctrl_csr_aliasing 7.420s 2182.564us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.290s 108.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
otp_ctrl_tl_intg_err 13.110s 2930.255us 1 1 100.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.110s 2930.255us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_kdi_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_part_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_macro_errs 3.220s 112.475us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_timer_fsm_local_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_kdi_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_part_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_macro_errs 3.220s 112.475us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 0 1 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
sec_cm_timer_fsm_global_esc 0 2 0.00
otp_ctrl_parallel_lc_esc 1.790s 46.020us 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.670s 118.583us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 25.390s 1628.539us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 14.910s 1110.362us 0 1 0.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 243.870s 200000.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.160s 2933.189us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.080s 612.625us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 3.220s 112.475us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 69.870s 26270.119us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 87.520s 36904.280us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 4 test runs
otp_ctrl_background_chks 104636200698790327383615780749938295679286553214931020046580577714072246358538 2884
UVM_INFO @ 1229822159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_lc_esc 36547510783840389094870560192273983539572047003064993999499047737838797720040 332
UVM_INFO @ 46019975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78868265260839659079309041234909877123181648802913047368865198189698584908828 19934
UVM_INFO @ 1628539155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 16571873548416396548697430149041006914489210777183673521424167511105687400685 2396
UVM_INFO @ 112475151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 2 test runs
otp_ctrl_test_access 112303710175851271333922590857634997618879365365555658115966273068562284310840 4705
UVM_INFO @ 206857504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 58670443694849765501660809952263541618663237638595242070387350015223810833346 12434
UVM_INFO @ 10352011817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 62826915413102347181997299787863012489824689966757782943608477250645387494027 110261
UVM_INFO @ 7831441850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 2605749575975898568673522800452629692666854104055604735868689063344226874844 89
UVM_INFO @ 26270118624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_dai_lock 67935797270816514192440567953386593690842499681404628907202287339791246162107 12122
UVM_INFO @ 1110362050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 96453973620025680081671466575097347078645000489773498956891435318033997027326 13621
UVM_INFO @ 36904279529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
otp_ctrl_sec_cm 52303097202838764687919001657525906917725174259153324750363500547500615552951 2833
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---