Simulation Results: rom_ctrl/64kb

 
07/07/2026 19:48:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.02 %
  • code
  • 91.06 %
  • assert
  • 97.53 %
  • func
  • 96.47 %
  • block
  • 96.05 %
  • line
  • 96.80 %
  • branch
  • 92.74 %
  • toggle
  • 84.23 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.000s 456.968us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 1024.108us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.000s 1980.272us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 546.710us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 216.599us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.000s 305.793us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.000s 1980.272us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 216.599us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 14048.311us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 305.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 4.000s 662.665us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.000s 2660.289us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 6213.355us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.000s 370.181us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 1495.758us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.000s 1495.758us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 1024.108us 1 1 100.00
rom_ctrl_csr_rw 6.000s 1980.272us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 216.599us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 216.303us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 1024.108us 1 1 100.00
rom_ctrl_csr_rw 6.000s 1980.272us 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 216.599us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 216.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 753.341us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
rom_ctrl_tl_intg_err 45.000s 2397.902us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.000s 456.968us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.000s 456.968us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.000s 456.968us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 45.000s 2397.902us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
rom_ctrl_kmac_err_chk 12.000s 6213.355us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 62.000s 2394.905us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 15.000s 753.341us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 108.000s 1731.209us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 35.000s 21225.896us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 25907578035860747865257877044309326470476224235056776018635172138031976745187 88
UVM_INFO @ 662665056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---